C3 support w/o ARB_DIS (P4-M on i845)

C3 support w/o ARB_DIS (P4-M on i845)

[Karol Kozimor]

Hi,
I've just noticed that FADT shows:
P_LVL2_LAT:       90
P_LVL3_LAT:       300

for my P4-M processor, whereas /proc/acpi/processor/*/power shows:
active state:            C2
default state:           C1
bus master activity:     00000000
states:
    C1:                  promotion[C2] demotion[--] latency[000] usage[00294320]
   *C2:                  promotion[--] demotion[C1] latency[090] usage[02552774]
    C3:                  <not supported>

and /proc/acpi/processor/*/info shows:
processor id:            0
acpi id:                 1
bus mastering control:   no
power management:        yes
throttling control:      yes
performance management:  yes
limit interface:         yes

So, it seems there is some C3 support, but it is not used due to lack of
bus-mastering control (PM2_CNT_BLK is 0). However, the flags section in the
FADT indicates that WBINVD is supported. The comment in processor.c says
the possibility of using C3 in the absence of ARB_DIS must be investigated.
What is the current status? Any obvious caveats for implementation?
Best regards,

-- 
Karol 'sziwan' Kozimor
sziwan-DETuoxkZsSqrDJvtcaxF/A@public.gmane.org


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Re: C3 support w/o ARB_DIS (P4-M on i845)

[Dominik Brodowski]

On Wed, May 12, 2004 at 12:25:27PM +0200, Karol Kozimor wrote:
> So, it seems there is some C3 support, but it is not used due to lack of
> bus-mastering control (PM2_CNT_BLK is 0). However, the flags section in the
> FADT indicates that WBINVD is supported. The comment in processor.c says
> the possibility of using C3 in the absence of ARB_DIS must be investigated.
> What is the current status? Any obvious caveats for implementation?

Well, there had been some discussion about that approximately two years ago,
maybe it's still in the archives. Major problems, IIRC:

a) occasional hangs on my system
b) unpredictable time of execution of WBINVD command (results in high latency)

I had posted some implementation back then, don't know whether it still
works. If you can't find it, contact me again, please.

	Dominik


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Re: C3 support w/o ARB_DIS (P4-M on i845)

[Karol Kozimor]

Thus wrote Dominik Brodowski:
> Well, there had been some discussion about that approximately two years ago,
> maybe it's still in the archives. Major problems, IIRC:
> 
> a) occasional hangs on my system
> b) unpredictable time of execution of WBINVD command (results in high latency)
> 
> I had posted some implementation back then, don't know whether it still
> works. If you can't find it, contact me again, please.

OK, I find the discussion, thanks for pointing that out. that out. Related
question: the ICH3-M spec specifies the PM2_CNT address at PMBASE + 0x20,
just before the GPE block. This seems consistent with my FADT, which places
PMBASE at 0xe400 and GPE0_BLK at 0xe428. Would manual poking at the
presumed location of ARB_DIS or FADT override work?
Best regards,

-- 
Karol 'sziwan' Kozimor
sziwan-DETuoxkZsSqrDJvtcaxF/A@public.gmane.org


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Re: C3 support w/o ARB_DIS (P4-M on i845)

[Dominik Brodowski]

On Wed, May 12, 2004 at 09:55:47PM +0200, Karol Kozimor wrote:
> question: the ICH3-M spec specifies the PM2_CNT address at PMBASE + 0x20,
> just before the GPE block. This seems consistent with my FADT, which places
> PMBASE at 0xe400 and GPE0_BLK at 0xe428. Would manual poking at the
> presumed location of ARB_DIS or FADT override work?

Maybe. On the other hand, your BIOS / hardware vendor likely disallowed C3
for a reason, e.g. some hardware which doesn't work flawlessly with ARB_DIS.
Note, for example, that the ipw2100 project ( http://ipw2100.sf.net )
suffers from some strange C3-related errors.

	Dominik


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Re: C3 support w/o ARB_DIS (P4-M on i845)

[Len Brown]

> On the other hand, your BIOS / hardware vendor likely disallowed C3
> for a reason, e.g. some hardware which doesn't work flawlessly with ARB_DIS.
> Note, for example, that the ipw2100 project ( http://ipw2100.sf.net )
> suffers from some strange C3-related errors.

I believe that this is a device-specific issue caused by inability
to deal with DMA buffer overflow/underruns that occur due to the
delays related to coming out of C3.

-Len




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