C2/C3 don't do anything

C2/C3 don't do anything

[Tony Lindgren]

Hi all,

I've been playing with Dynamic Tick, where the system timer is
stopped for the idle ticks. This allows the system to stay in sleep
mode inbetween the skipped ticks. [1] The most recent patch for
dynamic-tick is [2]

This works fine on ARM OMAP, but on my i386 boxes I've noticed that
only hlt works, C2 and C3 just spin in a busy loop and consume more
power than C1 with hlt!

I've done an idle module few years ago that enables C2 for dual
Athlon boxes [3], and that involved enabling it in the southbridge.

I thought the current ACPI code enables this already? But it does
not seem to be the case?

Should we have some extra code to scan the southbridges, or what is
the official way of handling that? It would be nice to get it
enabled...

At least my Crusoe based laptop with ALi 1533 chipset and Ali M7101
PMU does not get enabled. (Does anybody have docs to enable it on
1533/1535/7101???)

Cheers,

Tony

[1] http://lkml.org/lkml/2005/1/27/270
[2] http://lkml.org/lkml/2005/1/27/270
[3] http://muru.com/linux/amd-smp-idle/


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Re: C2/C3 don't do anything

[Dominik Brodowski]

Hi,

On Wed, Feb 02, 2005 at 07:46:40PM -0800, Tony Lindgren wrote:
> I've done an idle module few years ago that enables C2 for dual
> Athlon boxes [3], and that involved enabling it in the southbridge.
> 
> I thought the current ACPI code enables this already? But it does
> not seem to be the case?

AFAIK, if there is no initialization method included in the ACPI table, the
ACPI code does _not_ currently enables some special, vendor-specific bit in 
southbridges.

> Should we have some extra code to scan the southbridges,

Definitely. There is already some "errata" handling in the processor module,
possibly this could get extended.

	Dominik


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Re: C2/C3 don't do anything

[Karol Kozimor]

Thus wrote Dominik Brodowski:
> > I've done an idle module few years ago that enables C2 for dual
> > Athlon boxes [3], and that involved enabling it in the southbridge.
> > 
> > I thought the current ACPI code enables this already? But it does
> > not seem to be the case?
> 
> AFAIK, if there is no initialization method included in the ACPI table, the
> ACPI code does _not_ currently enables some special, vendor-specific bit in 
> southbridges.
> 
> > Should we have some extra code to scan the southbridges,
> 
> Definitely. There is already some "errata" handling in the processor module,
> possibly this could get extended.

I'm still using the patch to enable C3 on ICHx-M I once posted. Basically,
it provided a valid PM2_CNT_BLK address in case the OEM had forgotten to do
that, which in turn enabled C3 by providing a valid ARB_DIS address
(provided P_LVL3_LAT is valid).

It might be worthwile to add some quirks, possibly opt-in by a commandline
option.

Best regards,

-- 
Karol 'sziwan' Kozimor
sziwan-DETuoxkZsSqrDJvtcaxF/A@public.gmane.org


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Re: C2/C3 don't do anything

[Tony Lindgren]

* Karol Kozimor <sziwan-DETuoxkZsSqrDJvtcaxF/A@public.gmane.org> [050204 13:34]:
> Thus wrote Dominik Brodowski:
> > > I've done an idle module few years ago that enables C2 for dual
> > > Athlon boxes [3], and that involved enabling it in the southbridge.
> > > 
> > > I thought the current ACPI code enables this already? But it does
> > > not seem to be the case?
> > 
> > AFAIK, if there is no initialization method included in the ACPI table, the
> > ACPI code does _not_ currently enables some special, vendor-specific bit in 
> > southbridges.

OK, can you point me to the file to add printk's in the ACPI code where
the initialization happens? I'm not too familiar with ACPI code...

> > > Should we have some extra code to scan the southbridges,
> > 
> > Definitely. There is already some "errata" handling in the processor module,
> > possibly this could get extended.
> 
> I'm still using the patch to enable C3 on ICHx-M I once posted. Basically,
> it provided a valid PM2_CNT_BLK address in case the OEM had forgotten to do
> that, which in turn enabled C3 by providing a valid ARB_DIS address
> (provided P_LVL3_LAT is valid).

I have some code for the amd76x_pm module that can be modified for
scanning various southbridges. And then add functions for the
to enable them. I don't know when I'll have time to play with that
though.

This could be a separate module to start with, and then get integrated
into the ACPI code later on.

> It might be worthwile to add some quirks, possibly opt-in by a commandline
> option.

Or it could be an ACPI southbridge module?

Tony


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Re: C2/C3 don't do anything

[Dominik Brodowski]

On Fri, Feb 04, 2005 at 02:55:28PM -0800, Tony Lindgren wrote:
> > > > Should we have some extra code to scan the southbridges,
> > > 
> > > Definitely. There is already some "errata" handling in the processor module,
> > > possibly this could get extended.
> > 
> > I'm still using the patch to enable C3 on ICHx-M I once posted. Basically,
> > it provided a valid PM2_CNT_BLK address in case the OEM had forgotten to do
> > that, which in turn enabled C3 by providing a valid ARB_DIS address
> > (provided P_LVL3_LAT is valid).
> 
> I have some code for the amd76x_pm module that can be modified for
> scanning various southbridges. And then add functions for the
> to enable them. I don't know when I'll have time to play with that
> though.
> 
> This could be a separate module to start with, and then get integrated
> into the ACPI code later on.

Or this could be an extension of
drivers/acpi/processor_core.c::acpi_processor_errata() from the beginning.
Len, what do you think?

	Dominik


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