From mboxrd@z Thu Jan 1 00:00:00 1970 From: Matthew Garrett Subject: Re: [RFC][PATCH 4/4] PCI/ACPI PM: Propagate wake-up enable for devices w/o ACPI support Date: Fri, 4 Sep 2009 23:06:34 +0100 Message-ID: <20090904220634.GA32278@srcf.ucam.org> References: <200908300041.14541.rjw@sisk.pl> <200909041639.46289.rjw@sisk.pl> <20090904145638.GA23091@srcf.ucam.org> <200909050000.32288.rjw@sisk.pl> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <200909050000.32288.rjw@sisk.pl> Sender: linux-pci-owner@vger.kernel.org To: "Rafael J. Wysocki" Cc: ykzhao , "linux-pm@lists.linux-foundation.org" , ACPI Devel Maling List , Henrique de Moraes Holschuh , Jesse Barnes , Linux PCI List-Id: linux-acpi@vger.kernel.org On Sat, Sep 05, 2009 at 12:00:32AM +0200, Rafael J. Wysocki wrote: > > Yes, it's presumably the case that the PME event in the bridge is just > > tied to the root bridge in the chipset. Do we know what chipset this > > hardware is? For Intel, at least, GPE behaviour is defined in the > > chipset docs. > > One box is Intel, the other one is based on an ATI (pre-AMD) chipset, but > the design is similar in that respect. GPE 0xb will be the one generated by any Intel chipset whenever the external PCI PME# goes active. 0xd is the equivalent for chipset-level devices that don't have a GPE of their own. I can't see any way that a downstream bridge could reasonably generate a GPE, so I'd bet that it's using 0xb. -- Matthew Garrett | mjg59@srcf.ucam.org