From mboxrd@z Thu Jan 1 00:00:00 1970 From: Will Deacon Subject: Re: [PATCH v7 00/17] Introduce ACPI for ARM64 based on ACPI 5.1 Date: Fri, 16 Jan 2015 14:55:45 +0000 Message-ID: <20150116145545.GR7091@arm.com> References: <1421247905-3749-1-git-send-email-hanjun.guo@linaro.org> <20150115182346.GE2329@e104818-lin.cambridge.arm.com> <54B8BB24.2020408@linaro.org> <54B9240A.7060003@amd.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Received: from foss-mx-na.foss.arm.com ([217.140.108.86]:36142 "EHLO foss-mx-na.foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756491AbbAPOzw (ORCPT ); Fri, 16 Jan 2015 09:55:52 -0500 Content-Disposition: inline In-Reply-To: <54B9240A.7060003@amd.com> Sender: linux-acpi-owner@vger.kernel.org List-Id: linux-acpi@vger.kernel.org To: Tom Lendacky Cc: "hanjun.guo@linaro.org" , Catalin Marinas , "grant.likely@linaro.org" , Mark Rutland , linaro-acpi , Yijing Wang , Rob Herring , Lorenzo Pieralisi , Timur Tabi , ACPI Devel Mailing List , Charles Garcia-Tobin , "phoenix.liyi@huawei.com" , Robert Richter , Jason Cooper , Arnd Bergmann , Marc Zyngier , "jcm@redhat.com" , Mark Brown , Bjorn Helgaas , "linux-arm-kernel@lists.infradead.org" , graeme.gregory@ Hi Tom, On Fri, Jan 16, 2015 at 02:45:30PM +0000, Tom Lendacky wrote: > I have tested ACPI-enablement patches for the amd-xgbe/amd-xgbe-phy > drivers that I'm about to submit upstream with the V7 patch series > on the AMD Seattle server platform. There does not appear to be support > for the _CCA attribute in this patch series. The amd-xgbe driver will > setup the device domain and cache attributes based on the presence of > this attribute, but it requires the arch support to assign the proper > DMA operations in order for it to all work correctly. > > Overriding the _CCA attribute in the driver, I was able to successfully > test the driver and this patch series. Hopefully this will all be addressed when the IORT parts of ACPI have settled down (the current proposal allows for these attributes to be described as well as their interaction with things like IOMMUs). In the meantime, are you falling back to non-coherent DMA? If so, what attributes have you settled on? We need to be really careful not to corrupt data during cache invalidatation when mapping a non-coherent buffer for the CPU. Will