From mboxrd@z Thu Jan  1 00:00:00 1970
From: Catalin Marinas <catalin.marinas@arm.com>
Subject: Re: [PATCH v7 06/17] ARM64 / ACPI: Make PCI optional for ACPI on
 ARM64
Date: Mon, 19 Jan 2015 10:42:40 +0000
Message-ID: <20150119104240.GE11835@e104818-lin.cambridge.arm.com>
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 <20150116094913.GA13634@e104818-lin.cambridge.arm.com>
 <54BB51F1.8000900@linaro.org>
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To: Hanjun Guo <hanjun.guo@linaro.org>
Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net>, Olof Johansson <olof@lixom.net>, Arnd Bergmann <arnd@arndb.de>, Mark Rutland <Mark.Rutland@arm.com>, "grant.likely@linaro.org" <grant.likely@linaro.org>, Will Deacon <Will.Deacon@arm.com>, Lorenzo Pieralisi <Lorenzo.Pieralisi@arm.com>, "graeme.gregory@linaro.org" <graeme.gregory@linaro.org>, Sudeep Holla <Sudeep.Holla@arm.com>, "jcm@redhat.com" <jcm@redhat.com>, Jason Cooper <jason@lakedaemon.net>, Marc Zyngier <Marc.Zyngier@arm.com>, Bjorn Helgaas <bhelgaas@google.com>, Mark Brown <broonie@kernel.org>, Rob Herring <robh@kernel.org>, Robert Richter <rric@kernel.org>, Randy Dunlap <rdunlap@infradead.org>, Charles Garcia-Tobin <Charles.Garcia-Tobin@arm.com>, "phoenix.liyi@huawei.com" <phoenix.liyi@huawei.com>, Timur Tabi <timur@codeaurora.org>, "suravee.suthikulpanit@amd.com" <suravee.suthikulpanit@amd.com>, wangyijing@huawei
List-Id: linux-acpi@vger.kernel.org

On Sun, Jan 18, 2015 at 06:25:53AM +0000, Hanjun Guo wrote:
> On 2015=E5=B9=B401=E6=9C=8816=E6=97=A5 17:49, Catalin Marinas wrote:
> > On Wed, Jan 14, 2015 at 03:04:54PM +0000, Hanjun Guo wrote:
> >> --- a/arch/arm64/kernel/pci.c
> >> +++ b/arch/arm64/kernel/pci.c
> >> @@ -10,6 +10,7 @@
> >>    *
> >>    */
> >>
> >> +#include <linux/acpi.h>
> >>   #include <linux/init.h>
> >>   #include <linux/io.h>
> >>   #include <linux/kernel.h>
> >> @@ -68,3 +69,30 @@ void pci_bus_assign_domain_nr(struct pci_bus *b=
us, struct device *parent)
> >>   	bus->domain_nr =3D domain;
> >>   }
> >>   #endif
> >> +
> >> +/*
> >> + * raw_pci_read/write - Platform-specific PCI config space access=
=2E
> >> + *
> >> + * Default empty implementation.  Replace with an architecture-sp=
ecific setup
> >> + * routine, if necessary.
> >> + */
> >> +int raw_pci_read(unsigned int domain, unsigned int bus,
> >> +		  unsigned int devfn, int reg, int len, u32 *val)
> >> +{
> >> +	return -EINVAL;
> >> +}
> >> +
> >> +int raw_pci_write(unsigned int domain, unsigned int bus,
> >> +		unsigned int devfn, int reg, int len, u32 val)
> >> +{
> >> +	return -EINVAL;
> >> +}
> >> +
> >> +#ifdef CONFIG_ACPI
> >> +/* Root bridge scanning */
> >> +struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root)
> >> +{
> >> +	/* TODO: Should be revisited when implementing PCI on ACPI */
> >> +	return NULL;
> >> +}
> >> +#endif
[...]
> > When PCI is enabled and the above functions are compiled in, do the=
y
> > need to return any useful data or just -EINVAL. Are they ever calle=
d?
>=20
> They will be called if PCI root bridge is defined in DSDT, should I
> print some warning message before it is implemented?

My point: do they need to return real data when a PCI root bridge is
defined in DSDT or you always expect them to always return some -E*? Ca=
n
you explain why?

--=20
Catalin