From mboxrd@z Thu Jan 1 00:00:00 1970 From: Catalin Marinas Subject: Re: [PATCH v7 06/17] ARM64 / ACPI: Make PCI optional for ACPI on ARM64 Date: Tue, 20 Jan 2015 11:00:45 +0000 Message-ID: <20150120110045.GD25575@e104818-lin.cambridge.arm.com> References: <1421247905-3749-1-git-send-email-hanjun.guo@linaro.org> <1421247905-3749-7-git-send-email-hanjun.guo@linaro.org> <20150116094913.GA13634@e104818-lin.cambridge.arm.com> <54BB51F1.8000900@linaro.org> <20150119104240.GE11835@e104818-lin.cambridge.arm.com> <54BDBFD4.7050207@linaro.org> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: Content-Disposition: inline In-Reply-To: <54BDBFD4.7050207@linaro.org> Sender: linux-kernel-owner@vger.kernel.org To: Hanjun Guo Cc: "Rafael J. Wysocki" , Olof Johansson , Arnd Bergmann , Mark Rutland , "grant.likely@linaro.org" , Will Deacon , Lorenzo Pieralisi , "graeme.gregory@linaro.org" , Sudeep Holla , "jcm@redhat.com" , Jason Cooper , Marc Zyngier , Bjorn Helgaas , Mark Brown , Rob Herring , Robert Richter , Randy Dunlap , Charles Garcia-Tobin , "phoenix.liyi@huawei.com" , Timur Tabi , "suravee.suthikulpanit@amd.com" , wangyijing@huawei List-Id: linux-acpi@vger.kernel.org On Tue, Jan 20, 2015 at 02:39:16AM +0000, Hanjun Guo wrote: > On 2015=E5=B9=B401=E6=9C=8819=E6=97=A5 18:42, Catalin Marinas wrote: > > On Sun, Jan 18, 2015 at 06:25:53AM +0000, Hanjun Guo wrote: > >> On 2015=E5=B9=B401=E6=9C=8816=E6=97=A5 17:49, Catalin Marinas wrot= e: > >>> On Wed, Jan 14, 2015 at 03:04:54PM +0000, Hanjun Guo wrote: > >>>> --- a/arch/arm64/kernel/pci.c > >>>> +++ b/arch/arm64/kernel/pci.c > >>>> @@ -10,6 +10,7 @@ > >>>> * > >>>> */ > >>>> > >>>> +#include > >>>> #include > >>>> #include > >>>> #include > >>>> @@ -68,3 +69,30 @@ void pci_bus_assign_domain_nr(struct pci_bus = *bus, struct device *parent) > >>>> bus->domain_nr =3D domain; > >>>> } > >>>> #endif > >>>> + > >>>> +/* > >>>> + * raw_pci_read/write - Platform-specific PCI config space acce= ss. > >>>> + * > >>>> + * Default empty implementation. Replace with an architecture-= specific setup > >>>> + * routine, if necessary. > >>>> + */ > >>>> +int raw_pci_read(unsigned int domain, unsigned int bus, > >>>> + unsigned int devfn, int reg, int len, u32 *val) > >>>> +{ > >>>> + return -EINVAL; > >>>> +} > >>>> + > >>>> +int raw_pci_write(unsigned int domain, unsigned int bus, > >>>> + unsigned int devfn, int reg, int len, u32 val) > >>>> +{ > >>>> + return -EINVAL; > >>>> +} > >>>> + > >>>> +#ifdef CONFIG_ACPI > >>>> +/* Root bridge scanning */ > >>>> +struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root) > >>>> +{ > >>>> + /* TODO: Should be revisited when implementing PCI on ACPI */ > >>>> + return NULL; > >>>> +} > >>>> +#endif > > [...] > >>> When PCI is enabled and the above functions are compiled in, do t= hey > >>> need to return any useful data or just -EINVAL. Are they ever cal= led? > >> > >> They will be called if PCI root bridge is defined in DSDT, should = I > >> print some warning message before it is implemented? > > > > My point: do they need to return real data when a PCI root bridge i= s > > defined in DSDT or you always expect them to always return some -E*= ? Can > > you explain why? >=20 > Not always return -E* or NULL; >=20 > For raw_pci_read/write(), they are needed to access the PCI config sp= ace > before the PCI root bus is created. so they will return 0 if access t= o > PCI config space is ok; pci_acpi_scan_root() will return root bus > pointer if it is successfully created. OK. So what's the plan for implementing these functions properly. For the raw_pci_read/write, the comment states "replace with an architecture-specific setup routine". What does this mean? =46or pci_acpi_scan_root(), at least the comment states a "TODO". Is th= ere anyone working on this or we don't expect servers with PCIe soon? --=20 Catalin