From mboxrd@z Thu Jan 1 00:00:00 1970 From: Robert Richter Subject: Re: [PATCH v3 0/7] Cavium ThunderX2 SMMUv3 errata workarounds Date: Sat, 6 May 2017 00:22:50 +0200 Message-ID: <20170505222250.GY16981@rric.localdomain> References: <1493986091-30521-1-git-send-email-gakula@caviumnetworks.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Received: from mail-sn1nam01on0071.outbound.protection.outlook.com ([104.47.32.71]:14112 "EHLO NAM01-SN1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751370AbdEEWXG (ORCPT ); Fri, 5 May 2017 18:23:06 -0400 Content-Disposition: inline In-Reply-To: <1493986091-30521-1-git-send-email-gakula@caviumnetworks.com> Sender: linux-acpi-owner@vger.kernel.org List-Id: linux-acpi@vger.kernel.org To: Geetha sowjanya Cc: will.deacon@arm.com, robin.murphy@arm.com, lorenzo.pieralisi@arm.com, hanjun.guo@linaro.org, sudeep.holla@arm.com, iommu@lists.linux-foundation.org, jcm@redhat.com, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, sgoutham@cavium.com, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org, geethasowjanya.akula@gmail.com, linu.cherian@cavium.com, Charles.Garcia-Tobin@arm.com On 05.05.17 17:38:04, Geetha sowjanya wrote: > From: Linu Cherian > > Cavium ThunderX2 SMMUv3 implementation has two Silicon Erratas. > 1. Errata ID #74 > SMMU register alias Page 1 is not implemented > 2. Errata ID #126 > SMMU doesnt support unique IRQ lines and also MSI for gerror, > eventq and cmdq-sync > > The following patchset does software workaround for these two erratas. > > This series is based on patchset. > https://www.spinics.net/lists/arm-kernel/msg578443.html > > Changes from v1: > Since the use of MIDR register is rejected and SMMU_IIDR is broken on this > silicon, as suggested by Will Deacon modified the patches to use ThunderX2 > SMMUv3 IORT model number to enable errata workaround. > > Changes from v2: > Updated "Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt" document with > new SMMU option used to enable errata workaround. > > Geetha Sowjanya (1): > iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #126 > > Linu Cherian (6): > iommu/arm-smmu-v3: Introduce smmu option PAGE0_REGS_ONLY for ThunderX2 > errata#74. > iommu/arm-smmu-v3: Do resource size checks based on SMMU option > PAGE0_REGS_ONLY > ACPICA: IORT: Add Cavium ThunderX2 SMMUv3 model definition. > iommu/arm-smmu-v3: For ACPI based device probing, set PAGE0_REGS_ONLY > option for ThunderX2 SMMUv3 implementations. > ACPI/IORT: Fixup SMMUv3 resource size for Cavium ThunderX2 SMMUv3 > model > arm64: Documentation: Add Cavium ThunderX2 SMMUv3 erratas This split into patches does not look reasonable to me. 1 patch only for each workaround should be sufficient. -Robert > > Documentation/arm64/silicon-errata.txt | 2 + > drivers/acpi/arm64/iort.c | 10 ++- > drivers/iommu/arm-smmu-v3.c | 122 ++++++++++++++++++++++++++------- > include/acpi/actbl2.h | 2 + > 4 files changed, 110 insertions(+), 26 deletions(-) > > -- > 1.8.3.1 >