linux-acpi.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Will Deacon <will.deacon@arm.com>
To: Shameerali Kolothum Thodi <shameerali.kolothum.thodi@huawei.com>
Cc: "lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
	"marc.zyngier@arm.com" <marc.zyngier@arm.com>,
	"sudeep.holla@arm.com" <sudeep.holla@arm.com>,
	"robin.murphy@arm.com" <robin.murphy@arm.com>,
	"hanjun.guo@linaro.org" <hanjun.guo@linaro.org>,
	Gabriele Paoloni <gabriele.paoloni@huawei.com>,
	John Garry <john.garry@huawei.com>,
	Linuxarm <linuxarm@huawei.com>,
	"linux-acpi@vger.kernel.org" <linux-acpi@vger.kernel.org>,
	"iommu@lists.linux-foundation.org"
	<iommu@lists.linux-foundation.org>,
	"Wangzhou (B)" <wangzhou1@hisilicon.com>,
	"Guohanjun (Hanjun Guo)" <guohanjun@huawei.com>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	"devel@acpica.org" <devel@acpica.org>
Subject: Re: [PATCH v3 2/2] iommu/arm-smmu-v3:Enable ACPI based HiSilicon erratum 161010801
Date: Fri, 14 Jul 2017 20:33:23 +0100	[thread overview]
Message-ID: <20170714193322.GH26488@arm.com> (raw)
In-Reply-To: <5FC3163CFD30C246ABAA99954A238FA83839DB59@FRAEML521-MBX.china.huawei.com>

On Wed, Jul 05, 2017 at 09:48:53AM +0000, Shameerali Kolothum Thodi wrote:
> 
> 
> > -----Original Message-----
> > From: Will Deacon [mailto:will.deacon@arm.com]
> > Sent: Tuesday, July 04, 2017 6:38 PM
> > To: Shameerali Kolothum Thodi
> > Cc: lorenzo.pieralisi@arm.com; marc.zyngier@arm.com;
> > sudeep.holla@arm.com; robin.murphy@arm.com; hanjun.guo@linaro.org;
> > Gabriele Paoloni; John Garry; Linuxarm; linux-acpi@vger.kernel.org;
> > iommu@lists.linux-foundation.org; Wangzhou (B); Guohanjun (Hanjun Guo);
> > linux-arm-kernel@lists.infradead.org; devel@acpica.org
> > Subject: Re: [PATCH v3 2/2] iommu/arm-smmu-v3:Enable ACPI based
> > HiSilicon erratum 161010801
> > 
> > On Fri, Jun 23, 2017 at 03:58:01PM +0100, shameer wrote:
> > > The HiSilicon erratum 161010801 describes the limitation of HiSilicon
> > > platforms Hip06/Hip07 to support the SMMU mappings for MSI
> > transactions.
> > >
> > > On these platforms GICv3 ITS translator is presented with the deviceID
> > > by extending the MSI payload data to 64 bits to include the deviceID.
> > > Hence, the PCIe controller on this platforms has to differentiate the
> > > MSI payload against other DMA payload and has to modify the MSI
> > payload.
> > > This basically makes it difficult for this platforms to have a SMMU
> > > translation for MSI.
> > >
> > > This patch implements a ACPI table based quirk to reserve the hw msi
> > > regions in the smmu-v3 driver which means these address regions will
> > > not be translated and will be excluded from iova allocations.
> > >
> > > Signed-off-by: shameer <shameerali.kolothum.thodi@huawei.com>
> > > ---
> > >  drivers/iommu/arm-smmu-v3.c | 30 ++++++++++++++++++++++++++----
> > >  1 file changed, 26 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-
> > v3.c
> > > index abe4b88..c9346f2 100644
> > > --- a/drivers/iommu/arm-smmu-v3.c
> > > +++ b/drivers/iommu/arm-smmu-v3.c
> > > @@ -597,6 +597,7 @@ struct arm_smmu_device {
> > >  	u32				features;
> > >
> > >  #define ARM_SMMU_OPT_SKIP_PREFETCH	(1 << 0)
> > > +#define ARM_SMMU_OPT_RESV_HW_MSI	(1 << 1)
> > >  	u32				options;
> > >
> > >  	struct arm_smmu_cmdq		cmdq;
> > > @@ -1904,14 +1905,34 @@ static void arm_smmu_get_resv_regions(struct
> > device *dev,
> > >  				      struct list_head *head)
> > >  {
> > >  	struct iommu_resv_region *region;
> > > +	struct arm_smmu_device *smmu;
> > > +	struct iommu_fwspec *fwspec = dev->iommu_fwspec;
> > >  	int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO;
> > > +	int resv = 0;
> > >
> > > -	region = iommu_alloc_resv_region(MSI_IOVA_BASE,
> > MSI_IOVA_LENGTH,
> > > -					 prot, IOMMU_RESV_SW_MSI);
> > > -	if (!region)
> > > +	smmu = arm_smmu_get_by_fwnode(fwspec->iommu_fwnode);
> > 
> > Does this callback actually get called without a prior ->add_device callback
> > for the master in question? If not, then we can already claw the structure
> > out via the iommu_priv field in the fwspec.
> 
> Thanks Will for going through this.
> 
> Yes, from the logs I have, it looks like _resv callback is always called after
>  ->add_device. I will double check this with vfio bind case as well.
> 
> And I guess, this is what you are proposing to retrieve the smmu,
> 
> master = dev->iommu_fwspec->iommu_priv;
> smmu = master->smmu;
> 
> > > +	if (WARN_ON(!smmu))
> >
> > Again, how does this trigger?
> > >  		return;
> > >
> > > -	list_add_tail(&region->list, head);
> > > +	if ((smmu->options & ARM_SMMU_OPT_RESV_HW_MSI)) {
> > > +
> > > +		if (!is_of_node(smmu->dev->fwnode))
> > > +			resv = iort_iommu_its_get_resv_regions(dev, head);
> > 
> > How does this work when we're not using ACPI? Shouldn't of vs ACPI be
> > abstracted from the driver?
> 
> At present ARM_SMMU_OPT_RESV_HW_MSI is only set for ACPI and  DT support for
> this is a low priority for us at the moment. Is the suggestion is to have a common function
> outside the smmu driver for _iommu_its_get_resv_regions() ? I am not sure what
> is the best way here. 

Right, something like that. The driver shouldn't need to care whether or not
it's using ACPI or DT when setting these options.

Will

  reply	other threads:[~2017-07-14 19:33 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-06-23 14:57 [PATCH v3 0/2] iommu/smmu-v3: Workaround for hisilicon 161010801 erratum(reserve HW MSI) shameer
2017-06-23 14:58 ` [PATCH v3 1/2] acpi:iort: Add an IORT helper function to reserve HW ITS address regions for IOMMU drivers shameer
2017-06-23 16:54   ` Lorenzo Pieralisi
2017-07-03  8:18     ` Shameerali Kolothum Thodi
2017-07-04 10:16       ` Lorenzo Pieralisi
2017-06-23 14:58 ` [PATCH v3 2/2] iommu/arm-smmu-v3:Enable ACPI based HiSilicon erratum 161010801 shameer
2017-07-04 17:38   ` Will Deacon
2017-07-05  9:48     ` Shameerali Kolothum Thodi
2017-07-14 19:33       ` Will Deacon [this message]
2017-07-19 10:48         ` Shameerali Kolothum Thodi
2017-07-20 14:31           ` Robin Murphy
2017-07-20 15:30             ` Shameerali Kolothum Thodi

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20170714193322.GH26488@arm.com \
    --to=will.deacon@arm.com \
    --cc=devel@acpica.org \
    --cc=gabriele.paoloni@huawei.com \
    --cc=guohanjun@huawei.com \
    --cc=hanjun.guo@linaro.org \
    --cc=iommu@lists.linux-foundation.org \
    --cc=john.garry@huawei.com \
    --cc=linux-acpi@vger.kernel.org \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linuxarm@huawei.com \
    --cc=lorenzo.pieralisi@arm.com \
    --cc=marc.zyngier@arm.com \
    --cc=robin.murphy@arm.com \
    --cc=shameerali.kolothum.thodi@huawei.com \
    --cc=sudeep.holla@arm.com \
    --cc=wangzhou1@hisilicon.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).