From mboxrd@z Thu Jan 1 00:00:00 1970 From: Greg Kroah-Hartman Subject: Re: [PATCH 4/7] node: Add memory caching attributes Date: Mon, 26 Nov 2018 20:06:52 +0100 Message-ID: <20181126190652.GB32595@kroah.com> References: <20181114224921.12123-2-keith.busch@intel.com> <20181114224921.12123-5-keith.busch@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <20181114224921.12123-5-keith.busch@intel.com> Sender: linux-kernel-owner@vger.kernel.org To: Keith Busch Cc: linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, linux-mm@kvack.org, Rafael Wysocki , Dave Hansen , Dan Williams List-Id: linux-acpi@vger.kernel.org On Wed, Nov 14, 2018 at 03:49:17PM -0700, Keith Busch wrote: > System memory may have side caches to help improve access speed. While > the system provided cache is transparent to the software accessing > these memory ranges, applications can optimize their own access based > on cache attributes. > > In preparation for such systems, provide a new API for the kernel to > register these memory side caches under the memory node that provides it. > > The kernel's sysfs representation is modeled from the cpu cacheinfo > attributes, as seen from /sys/devices/system/cpu/cpuX/cache/. Unlike CPU > cacheinfo, though, a higher node's memory cache level is nearer to the > CPU, while lower levels are closer to the backing memory. Also unlike > CPU cache, the system handles flushing any dirty cached memory to the > last level the memory on a power failure if the range is persistent. > > The exported attributes are the cache size, the line size, associativity, > and write back policy. You also didn't document your new sysfs attributes/layout in a Documentation/ABI/ entry which is required for any sysfs change... thanks, greg k-h