[PATCH v2 1/3] pinctrl: cherryview: Split out irq hw-init into a separate helper function

Hans de Goede
2019-11-06T15:47:27Z

Split out irq hw-init into a separate chv_gpio_irq_init_hw() function.
This is a preparation patch for passing the irqchip when adding the
gpiochip.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
Changes in v2:
- Add kerneldoc for chv_pinctrl.need_valid_mask struct member
---
drivers/pinctrl/intel/pinctrl-cherryview.c | 58 +++++++++++++---------
1 file changed, 35 insertions(+), 23 deletions(-)

diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c
index dff2a81250b6..3ae0d398368d 100644
--- a/drivers/pinctrl/intel/pinctrl-cherryview.c
+++ b/drivers/pinctrl/intel/pinctrl-cherryview.c
@@ -149,6 +149,7 @@ struct chv_pin_context {
* @chip: GPIO chip in this pin controller
* @irqchip: IRQ chip in this pin controller
* @regs: MMIO registers
+ * @need_valid_mask: Use chip.irq.init_valid_mask ?
* @intr_lines: Stores mapping between 16 HW interrupt wires and GPIO
* offset (in GPIO number space)
* @community: Community this pinctrl instance represents
@@ -165,6 +166,7 @@ struct chv_pinctrl {
struct gpio_chip chip;
struct irq_chip irqchip;
void __iomem *regs;
+ bool need_valid_mask;
unsigned intr_lines[16];
const struct chv_community *community;
u32 saved_intmask;
@@ -1555,13 +1557,40 @@ static void chv_init_irq_valid_mask(struct gpio_chip *chip,
}
}

+static int chv_gpio_irq_init_hw(struct gpio_chip *chip)
+{
+ struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
+
+ /*
+ * The same set of machines in chv_no_valid_mask[] have incorrectly
+ * configured GPIOs that generate spurious interrupts so we use
+ * this same list to apply another quirk for them.
+ *
+ * See also https://bugzilla.kernel.org/show_bug.cgi?id=197953.
+ */
+ if (!pctrl->need_valid_mask) {
+ /*
+ * Mask all interrupts the community is able to generate
+ * but leave the ones that can only generate GPEs unmasked.
+ */
+ chv_writel(GENMASK(31, pctrl->community->nirqs),
+ pctrl->regs + CHV_INTMASK);
+ }
+
+ /* Clear all interrupts */
+ chv_writel(0xffff, pctrl->regs + CHV_INTSTAT);
+
+ return 0;
+}
+
static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq)
{
const struct chv_gpio_pinrange *range;
struct gpio_chip *chip = &pctrl->chip;
- bool need_valid_mask = !dmi_check_system(chv_no_valid_mask);
const struct chv_community *community = pctrl->community;
- int ret, i, irq_base;
+ int ret, i, irq_base = 0;
+
+ pctrl->need_valid_mask = !dmi_check_system(chv_no_valid_mask);

*chip = chv_gpio_chip;

@@ -1569,7 +1598,7 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq)
chip->label = dev_name(pctrl->dev);
chip->parent = pctrl->dev;
chip->base = -1;
- if (need_valid_mask)
+ if (pctrl->need_valid_mask)
chip->irq.init_valid_mask = chv_init_irq_valid_mask;

ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl);
@@ -1589,26 +1618,9 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq)
}
}

- /*
- * The same set of machines in chv_no_valid_mask[] have incorrectly
- * configured GPIOs that generate spurious interrupts so we use
- * this same list to apply another quirk for them.
- *
- * See also https://bugzilla.kernel.org/show_bug.cgi?id=197953.
- */
- if (!need_valid_mask) {
- /*
- * Mask all interrupts the community is able to generate
- * but leave the ones that can only generate GPEs unmasked.
- */
- chv_writel(GENMASK(31, pctrl->community->nirqs),
- pctrl->regs + CHV_INTMASK);
- }
-
- /* Clear all interrupts */
- chv_writel(0xffff, pctrl->regs + CHV_INTSTAT);
+ chv_gpio_irq_init_hw(chip);

- if (!need_valid_mask) {
+ if (!pctrl->need_valid_mask) {
irq_base = devm_irq_alloc_descs(pctrl->dev, -1, 0,
community->npins, NUMA_NO_NODE);
if (irq_base < 0) {
@@ -1632,7 +1644,7 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq)
return ret;
}

- if (!need_valid_mask) {
+ if (!pctrl->need_valid_mask) {
for (i = 0; i < community->ngpio_ranges; i++) {
range = &community->gpio_ranges[i];

--
2.23.0