Re: [RFC] ACPI: PCC: Support shared interrupt for multiple subspaces

[Sudeep Holla <sudeep.holla@arm.com>]

On Fri, Nov 04, 2022 at 11:04:22AM -0400, Robbie King wrote:
> Hello Huisong, your raising of the shared interrupt issue is very timely, I
> am working to implement "Extended PCC subspaces (types 3 and 4)" using PCC
> on the ARM RDN2 reference platform as a proof of concept, and encountered
> this issue as well.  FWIW, I am currently testing using Sudeep's patch with
> the "chan_in_use" flag removed, and so far have not encountered any issues.
>

Interesting, do you mean the patch I post in this thread but without the
whole chan_in_use flag ?

> I think the RDN2 may provide an example of a write only interrupt
> acknowledge mechanism mentioned by Sudeep.
>

Yes.

> The RDN2 reference design uses the MHUv2 IP for the doorbell mechanism.  If
> my implementation is correct (and it quite possibly is not), acknowledging
> the DB interrupt from the platform is accomplished by writing a 1 to the
> appropriate bit in the receiver channel window CH_CLR register, which is
> documented as:
>
>   Channel flag clear.
>   Write 0b1 to a bit clears the corresponding bit in the CH_ST and CH_ST_MSK.
>   Writing 0b0 has no effect.
>   Each bit always reads as 0b0.
>

Correct, on this MHUv[1-2], it is write only register and it reads zero.
So basically you will ignore the interrupt if we apply the logic Huisong
proposed initially.

> in the "Arm Corstone SSE-700 Subsystem Technical Reference Manual".
>
> Apologies if I am off in the weeds here as I have only been working with
> PCC/SCMI for a very short period of time.

Good to know info :).

-- 
Regards,
Sudeep