From: Ben Cheatham <Benjamin.Cheatham@amd.com>
To: <rafael@kernel.org>, <dan.j.williams@intel.com>,
<linux-cxl@vger.kernel.org>, <linux-acpi@vger.kernel.org>
Cc: <bhelgaas@google.com>, <benjamin.cheatham@amd.com>,
<yazen.ghannam@amd.com>
Subject: [PATCH v5 0/3] CXL, ACPI, APEI, EINJ: Update EINJ for CXL 1.1 error types
Date: Mon, 25 Sep 2023 15:01:24 -0500 [thread overview]
Message-ID: <20230925200127.504256-1-Benjamin.Cheatham@amd.com> (raw)
v5 Changes:
- Removed device_add_file() in favor of using sysfs_create_group()
and an is_visible() callback
- Add setting cxl_root to NULL on cxl_acpi driver exit
- Add real path for cxl_rcrb_addr file to documentation in addition
to symlink path
This patch is a follow up to the discussion at [1], and builds on Tony's
CXL error patch at [2].
The new CXL error types will use the Memory Address field in the
SET_ERROR_TYPE_WITH_ADDRESS structure in order to target a CXL 1.1
compliant memory-mapped downstream port. The value of the memory address
will be in the port's MMIO range, and it will not represent physical
(normal or persistent) memory.
In v2 [3], the user supplied the MMIO address for the downstream port, but
per Dan Williams' suggestion [3], the addresses are predetermined and
the user only picks the error type to inject and the downstream port to
inject into. In order to inject an error, the user write the error type
to the error_type file under the einj debugfs directory, then writes any
integer into one of the files under the cxl directory.
[1]:
Link: https://lore.kernel.org/linux-acpi/20221206205234.606073-1-Benjamin.Cheatham@amd.com/
[2]:
Link: https://lore.kernel.org/linux-cxl/CAJZ5v0hNQUfWViqxbJ5B4JCGJUuHpWWSpqpCFWPNpGuagoFbsQ@mail.gmail.com/T/#t
[3]:
Link: https://lore.kernel.org/linux-cxl/20230403151849.43408-1-Benjamin.Cheatham@amd.com/
Ben Cheatham (3):
CXL, PCIE: Add cxl_rcrb_addr file to dport_dev
ACPI, APEI, EINJ: Add CXL 1.1 EINJ error type support
ACPI, APEI, EINJ: Update EINJ documentation
Documentation/ABI/testing/sysfs-bus-cxl | 9 +++
.../firmware-guide/acpi/apei/einj.rst | 25 ++++++-
drivers/acpi/apei/Kconfig | 2 +
drivers/acpi/apei/einj.c | 24 +++++-
drivers/cxl/acpi.c | 3 +
drivers/cxl/core/port.c | 75 +++++++++++++++++++
drivers/cxl/cxl.h | 3 +
include/linux/cxl.h | 11 +++
8 files changed, 147 insertions(+), 5 deletions(-)
create mode 100644 include/linux/cxl.h
--
2.34.1
next reply other threads:[~2023-09-25 20:01 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-25 20:01 Ben Cheatham [this message]
2023-09-25 20:01 ` [PATCH v5 1/3] CXL, PCIE: Add cxl_rcrb_addr file to dport_dev Ben Cheatham
2023-09-26 10:50 ` Jonathan Cameron
2023-09-26 16:00 ` Ben Cheatham
2023-09-26 20:23 ` Bjorn Helgaas
2023-09-27 15:30 ` Ben Cheatham
2023-09-26 21:15 ` Dan Williams
2023-09-27 15:31 ` Ben Cheatham
2023-09-25 20:01 ` [PATCH v5 2/3] ACPI, APEI, EINJ: Add CXL 1.1 EINJ error type support Ben Cheatham
2023-09-26 11:04 ` Jonathan Cameron
2023-09-26 16:00 ` Ben Cheatham
2023-09-26 20:22 ` Bjorn Helgaas
2023-09-27 15:31 ` Ben Cheatham
2023-09-26 21:36 ` Dan Williams
2023-09-27 15:32 ` Ben Cheatham
2023-09-25 20:01 ` [PATCH v5 3/3] ACPI, APEI, EINJ: Update EINJ documentation Ben Cheatham
2023-09-26 11:05 ` Jonathan Cameron
2023-09-26 16:00 ` Ben Cheatham
2023-09-26 20:24 ` Bjorn Helgaas
2023-09-27 15:31 ` Ben Cheatham
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