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From: Bjorn Helgaas <helgaas@kernel.org>
To: Ben Cheatham <Benjamin.Cheatham@amd.com>
Cc: rafael@kernel.org, dan.j.williams@intel.com,
	linux-cxl@vger.kernel.org, linux-acpi@vger.kernel.org,
	bhelgaas@google.com, yazen.ghannam@amd.com
Subject: Re: [PATCH v5 1/3] CXL, PCIE: Add cxl_rcrb_addr file to dport_dev
Date: Tue, 26 Sep 2023 15:23:43 -0500	[thread overview]
Message-ID: <20230926202343.GA419574@bhelgaas> (raw)
In-Reply-To: <20230925200127.504256-2-Benjamin.Cheatham@amd.com>

On Mon, Sep 25, 2023 at 03:01:25PM -0500, Ben Cheatham wrote:
> Add cxl_rcrb_addr to the dport_dev (normally represented by a pcie
> device) for CXL RCH root ports. The file will print the RCRB base
> MMIO address of the root port when read and will be used by
> users looking to inject CXL EINJ error types for RCH hosts.

I guess this is talking about a sysfs file?  If so, maybe mention that
explicitly in the subject and commit log.

I don't know how you decided to capitalize CXL initialisms and not
"pcie", but I usually use "PCIe".  

> +static struct cxl_port *cxl_root;
> +
> +void set_cxl_root(struct cxl_port *root_port)
> +{
> +	cxl_root = root_port;
> +}

Is there always at most one cxl_root?  Seems worth a one-line comment
at the static data item, since in the world of devices, data is
usually in a per-device struct, not in a single static item.

> @@ -1021,6 +1074,11 @@ __devm_cxl_add_dport(struct cxl_port *port, struct device *dport_dev,
>  	if (rc)
>  		return ERR_PTR(rc);
>  
> +	rc = sysfs_create_group(&dport_dev->kobj, &cxl_rcrb_addr_group);
> +	if (rc)
> +		dev_dbg(dport_dev, "Couldn't create cxl_rcrb_addr group: %d\n",
> +			rc);

Is there any way to create this with an attribute group that the sysfs
infrastructure adds automatically?  I'm not suggesting you have a race
condition here, but using the sysfs infrastructure avoids a lot of
potential problems.

Bjorn

  parent reply	other threads:[~2023-09-26 20:23 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-09-25 20:01 [PATCH v5 0/3] CXL, ACPI, APEI, EINJ: Update EINJ for CXL 1.1 error types Ben Cheatham
2023-09-25 20:01 ` [PATCH v5 1/3] CXL, PCIE: Add cxl_rcrb_addr file to dport_dev Ben Cheatham
2023-09-26 10:50   ` Jonathan Cameron
2023-09-26 16:00     ` Ben Cheatham
2023-09-26 20:23   ` Bjorn Helgaas [this message]
2023-09-27 15:30     ` Ben Cheatham
2023-09-26 21:15   ` Dan Williams
2023-09-27 15:31     ` Ben Cheatham
2023-09-25 20:01 ` [PATCH v5 2/3] ACPI, APEI, EINJ: Add CXL 1.1 EINJ error type support Ben Cheatham
2023-09-26 11:04   ` Jonathan Cameron
2023-09-26 16:00     ` Ben Cheatham
2023-09-26 20:22   ` Bjorn Helgaas
2023-09-27 15:31     ` Ben Cheatham
2023-09-26 21:36   ` Dan Williams
2023-09-27 15:32     ` Ben Cheatham
2023-09-25 20:01 ` [PATCH v5 3/3] ACPI, APEI, EINJ: Update EINJ documentation Ben Cheatham
2023-09-26 11:05   ` Jonathan Cameron
2023-09-26 16:00     ` Ben Cheatham
2023-09-26 20:24   ` Bjorn Helgaas
2023-09-27 15:31     ` Ben Cheatham

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