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From: Andrew Jones <ajones@ventanamicro.com>
To: Sunil V L <sunilvl@ventanamicro.com>
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	 linux-acpi@vger.kernel.org,
	Paul Walmsley <paul.walmsley@sifive.com>,
	 Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	 "Rafael J . Wysocki" <rafael@kernel.org>,
	Len Brown <lenb@kernel.org>,
	 Conor Dooley <conor.dooley@microchip.com>,
	Anup Patel <apatel@ventanamicro.com>,
	 Ard Biesheuvel <ardb@kernel.org>,
	Atish Kumar Patra <atishp@rivosinc.com>
Subject: Re: [PATCH v3 -next 3/3] RISC-V: cacheflush: Initialize CBO variables on ACPI systems
Date: Tue, 17 Oct 2023 10:41:02 +0200	[thread overview]
Message-ID: <20231017-e198b2c70475b6f09754d175@orel> (raw)
In-Reply-To: <20231016164958.1191529-4-sunilvl@ventanamicro.com>

On Mon, Oct 16, 2023 at 10:19:58PM +0530, Sunil V L wrote:
> Initialize the CBO variables on ACPI based systems using information in
> RHCT.
> 
> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> ---
>  arch/riscv/mm/cacheflush.c | 25 +++++++++++++++++++------
>  1 file changed, 19 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c
> index f1387272a551..55a34f2020a8 100644
> --- a/arch/riscv/mm/cacheflush.c
> +++ b/arch/riscv/mm/cacheflush.c
> @@ -3,7 +3,9 @@
>   * Copyright (C) 2017 SiFive
>   */
>  
> +#include <linux/acpi.h>
>  #include <linux/of.h>
> +#include <asm/acpi.h>
>  #include <asm/cacheflush.h>
>  
>  #ifdef CONFIG_SMP
> @@ -124,13 +126,24 @@ void __init riscv_init_cbo_blocksizes(void)
>  	unsigned long cbom_hartid, cboz_hartid;
>  	u32 cbom_block_size = 0, cboz_block_size = 0;
>  	struct device_node *node;
> +	struct acpi_table_header *rhct;
> +	acpi_status status;
> +
> +	if (acpi_disabled) {
> +		for_each_of_cpu_node(node) {
> +			/* set block-size for cbom and/or cboz extension if available */
> +			cbo_get_block_size(node, "riscv,cbom-block-size",
> +					   &cbom_block_size, &cbom_hartid);
> +			cbo_get_block_size(node, "riscv,cboz-block-size",
> +					   &cboz_block_size, &cboz_hartid);
> +		}
> +	} else {
> +		status = acpi_get_table(ACPI_SIG_RHCT, 0, &rhct);
> +		if (ACPI_FAILURE(status))
> +			return;
>  
> -	for_each_of_cpu_node(node) {
> -		/* set block-size for cbom and/or cboz extension if available */
> -		cbo_get_block_size(node, "riscv,cbom-block-size",
> -				   &cbom_block_size, &cbom_hartid);
> -		cbo_get_block_size(node, "riscv,cboz-block-size",
> -				   &cboz_block_size, &cboz_hartid);
> +		acpi_get_cbo_block_size(rhct, &cbom_block_size, &cboz_block_size, NULL);
> +		acpi_put_table((struct acpi_table_header *)rhct);
>  	}
>  
>  	if (cbom_block_size)
> -- 
> 2.39.2
>

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>

  reply	other threads:[~2023-10-17  8:41 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-16 16:49 [PATCH v3 -next 0/3] RISC-V: ACPI improvements Sunil V L
2023-10-16 16:49 ` [PATCH v3 -next 1/3] RISC-V: ACPI: Enhance acpi_os_ioremap with MMIO remapping Sunil V L
2023-10-16 16:49 ` [PATCH v3 -next 2/3] RISC-V: ACPI: RHCT: Add function to get CBO block sizes Sunil V L
2023-10-17  8:37   ` Andrew Jones
2023-10-17 15:39     ` Sunil V L
2023-10-17 17:03       ` Andrew Jones
2023-10-16 16:49 ` [PATCH v3 -next 3/3] RISC-V: cacheflush: Initialize CBO variables on ACPI systems Sunil V L
2023-10-17  8:41   ` Andrew Jones [this message]
2023-10-17 18:38   ` Samuel Holland

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