From: Ben Cheatham <Benjamin.Cheatham@amd.com>
To: <dan.j.williams@intel.com>, <dave@stogolabs.net>,
<jonathan.cameron@huawei.com>, <dave.jiang@intel.com>,
<alison.schofield@intel.com>, <vishal.l.verma@intel.com>,
<ira.weiny@intel.com>, <rafael@kernel.org>
Cc: <linux-cxl@vger.kernel.org>, <linux-acpi@vger.kernel.org>,
<benjamin.cheatham@amd.com>
Subject: [PATCH v8 5/5] EINJ, Documentation: Update EINJ kernel doc
Date: Wed, 13 Dec 2023 16:37:02 -0600 [thread overview]
Message-ID: <20231213223702.543419-6-Benjamin.Cheatham@amd.com> (raw)
In-Reply-To: <20231213223702.543419-1-Benjamin.Cheatham@amd.com>
Update EINJ kernel document to include how to inject CXL protocol error
types, build the kernel to include CXL error types, and give an example
injection.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Ben Cheatham <Benjamin.Cheatham@amd.com>
---
.../firmware-guide/acpi/apei/einj.rst | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/Documentation/firmware-guide/acpi/apei/einj.rst b/Documentation/firmware-guide/acpi/apei/einj.rst
index d6b61d22f525..a9d3f6926cae 100644
--- a/Documentation/firmware-guide/acpi/apei/einj.rst
+++ b/Documentation/firmware-guide/acpi/apei/einj.rst
@@ -181,6 +181,25 @@ You should see something like this in dmesg::
[22715.834759] EDAC sbridge MC3: PROCESSOR 0:306e7 TIME 1422553404 SOCKET 0 APIC 0
[22716.616173] EDAC MC3: 1 CE memory read error on CPU_SrcID#0_Channel#0_DIMM#0 (channel:0 slot:0 page:0x12345 offset:0x0 grain:32 syndrome:0x0 - area:DRAM err_code:0001:0090 socket:0 channel_mask:1 rank:0)
+CXL error types are supported from ACPI 6.5 onwards. These error types
+are not available in the legacy interface at /sys/kernel/debug/apei/einj,
+and are instead at /sys/kernel/debug/cxl/. There is a file under debug/cxl
+called "einj_type" that is analagous to available_error_type under debug/cxl.
+There is also a "einj_inject" file in each $dport_dev directory under debug/cxl
+that will inject a given error into the dport represented by $dport_dev.
+For example, to inject a CXL.mem protocol correctable error into
+$dport_dev=pci0000:0c::
+
+ # cd /sys/kernel/debug/cxl/
+ # cat einj_type # See which error can be injected
+ 0x00008000 CXL.mem Protocol Correctable
+ 0x00010000 CXL.mem Protocol Uncorrectable non-fatal
+ 0x00020000 CXL.mem Protocol Uncorrectable fatal
+ # cd pci0000:0c # Navigate to dport to inject into
+ # echo 0x8000 > einj_inject # Inject error
+
+To use CXL error types, ``CONFIG_CXL_EINJ`` will need to be enabled.
+
Special notes for injection into SGX enclaves:
There may be a separate BIOS setup option to enable SGX injection.
--
2.34.1
prev parent reply other threads:[~2023-12-13 22:38 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-13 22:36 [PATCH v8 0/5] CXL, ACPI, APEI, EINJ: Update EINJ for CXL error types Ben Cheatham
2023-12-13 22:36 ` [PATCH v8 1/5] cxl, ACPI, APEI, EINJ: Add CXL_EINJ Kconfig option Ben Cheatham
2023-12-18 23:48 ` Dan Williams
2024-01-10 20:31 ` Ben Cheatham
2023-12-13 22:36 ` [PATCH v8 2/5] ACPI, APEI, EINJ: Add wrapper __init function Ben Cheatham
2023-12-18 23:59 ` Dan Williams
2023-12-19 15:39 ` Jonathan Cameron
2023-12-19 20:48 ` Dan Williams
2023-12-20 14:37 ` Ben Cheatham
2023-12-20 23:51 ` Dan Williams
2023-12-20 14:33 ` Ben Cheatham
2023-12-13 22:37 ` [PATCH v8 3/5] ACPI: Add CXL protocol error defines Ben Cheatham
2023-12-19 5:09 ` Dan Williams
2023-12-13 22:37 ` [PATCH v8 4/5] cxl/core, EINJ: Add CXL debugfs files and EINJ functions Ben Cheatham
2023-12-19 4:47 ` Dan Williams
2024-01-10 20:31 ` Ben Cheatham
2024-01-10 22:10 ` Dan Williams
2024-01-10 22:17 ` Ben Cheatham
2023-12-13 22:37 ` Ben Cheatham [this message]
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