From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Dave Jiang <dave.jiang@intel.com>
Cc: <linux-cxl@vger.kernel.org>, <linux-acpi@vger.kernel.org>,
<dan.j.williams@intel.com>, <ira.weiny@intel.com>,
<vishal.l.verma@intel.com>, <alison.schofield@intel.com>,
<dave@stgolabs.net>, <rafael@kernel.org>,
<gregkh@linuxfoundation.org>
Subject: Re: [PATCH v5 03/12] ACPI: HMAT: Introduce 2 levels of generic port access class
Date: Thu, 15 Feb 2024 16:44:37 +0000 [thread overview]
Message-ID: <20240215164437.00005f86@Huawei.com> (raw)
In-Reply-To: <20240206222951.1833098-4-dave.jiang@intel.com>
On Tue, 6 Feb 2024 15:28:31 -0700
Dave Jiang <dave.jiang@intel.com> wrote:
> In order to compute access0 and access1 classes for CXL memory, 2 levels
> of generic port information must be stored. Access0 will indicate the
> generic port access coordinates to the closest initiator and access1
> will indicate the generic port access coordinates to the cloest CPU.
>
> Cc: Rafael J. Wysocki <rafael@kernel.org>
> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Grumble. I never liked Memory Proximity Domain Attributes Structure.
Adds little value and for ports I don't think you should consider it
(because it's about GI or Processor to Memory connections and
Generic Ports aren't allowed in either field).
Other than dropping that short cut, LGTM.
> ---
> drivers/acpi/numa/hmat.c | 18 ++++++++++++------
> 1 file changed, 12 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/acpi/numa/hmat.c b/drivers/acpi/numa/hmat.c
> index e0144cfbf1f3..8dbb0e366059 100644
> --- a/drivers/acpi/numa/hmat.c
> +++ b/drivers/acpi/numa/hmat.c
> @@ -59,7 +59,8 @@ struct target_cache {
> };
>
> enum {
> - NODE_ACCESS_CLASS_GENPORT_SINK = ACCESS_COORDINATE_MAX,
> + NODE_ACCESS_CLASS_GENPORT_SINK_LOCAL = ACCESS_COORDINATE_MAX,
> + NODE_ACCESS_CLASS_GENPORT_SINK_CPU,
> NODE_ACCESS_CLASS_MAX,
> };
>
> @@ -141,7 +142,7 @@ int acpi_get_genport_coordinates(u32 uid,
> if (!target)
> return -ENOENT;
>
> - *coord = target->coord[NODE_ACCESS_CLASS_GENPORT_SINK];
> + *coord = target->coord[NODE_ACCESS_CLASS_GENPORT_SINK_LOCAL];
>
> return 0;
> }
> @@ -695,7 +696,8 @@ static void hmat_update_target_attrs(struct memory_target *target,
> int i;
>
> /* Don't update for generic port if there's no device handle */
> - if (access == NODE_ACCESS_CLASS_GENPORT_SINK &&
> + if ((access == NODE_ACCESS_CLASS_GENPORT_SINK_LOCAL ||
> + access == NODE_ACCESS_CLASS_GENPORT_SINK_CPU) &&
> !(*(u16 *)target->gen_port_device_handle))
> return;
>
> @@ -707,7 +709,8 @@ static void hmat_update_target_attrs(struct memory_target *target,
> */
> if (target->processor_pxm != PXM_INVAL) {
> cpu_nid = pxm_to_node(target->processor_pxm);
> - if (access == ACCESS_COORDINATE_LOCAL ||
> + if ((access == ACCESS_COORDINATE_LOCAL ||
> + access == NODE_ACCESS_CLASS_GENPORT_SINK_LOCAL) &&
The comment above this says:
/*
* If the Address Range Structure provides a local processor pxm, set
* only that one. Otherwise, find the best performance attributes and
* collect all initiators that match.
*/
Assuming that is correct, under what circumstances is it relevant to a
generic port? I'm hoping no one builds systems with RAM that is local to
a port?
Note that the comment requires some archaeology - the Address Range structure
has been renamed as Memory Proximity Domain Attributes Structure. (see ACPI 6.2)
And the 'local processor PXM was probably originally Processor Proximity Domain.
That has now become "Proximity Domain for the Attached Initiator." It's
used only basically override the HMAT distances and say:
Memory domain X is directly attached to Processor Y
Here we don't have a memory domain (generic port) and so I don't think that
case is relevant.
So leave this block alone.
> node_state(cpu_nid, N_CPU)) {
> set_bit(target->processor_pxm, p_nodes);
> return;
> @@ -736,7 +739,8 @@ static void hmat_update_target_attrs(struct memory_target *target,
> list_for_each_entry(initiator, &initiators, node) {
> u32 value;
>
> - if (access == ACCESS_COORDINATE_CPU &&
> + if ((access == ACCESS_COORDINATE_CPU &&
> + access == NODE_ACCESS_CLASS_GENPORT_SINK_CPU) &&
This one looks to be correct.
> !initiator->has_cpu) {
> clear_bit(initiator->processor_pxm, p_nodes);
> continue;
> @@ -775,7 +779,9 @@ static void hmat_update_generic_target(struct memory_target *target)
> static DECLARE_BITMAP(p_nodes, MAX_NUMNODES);
>
> hmat_update_target_attrs(target, p_nodes,
> - NODE_ACCESS_CLASS_GENPORT_SINK);
> + NODE_ACCESS_CLASS_GENPORT_SINK_LOCAL);
> + hmat_update_target_attrs(target, p_nodes,
> + NODE_ACCESS_CLASS_GENPORT_SINK_CPU);
> }
>
> static void hmat_register_target_initiators(struct memory_target *target)
next prev parent reply other threads:[~2024-02-15 16:44 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-06 22:28 [PATCH v5 0/12] cxl: Add support to report region access coordinates to numa nodes Dave Jiang
2024-02-06 22:28 ` [PATCH v5 01/12] ACPI: HMAT: Remove register of memory node for generic target Dave Jiang
2024-02-15 16:20 ` Jonathan Cameron
2024-02-06 22:28 ` [PATCH v5 02/12] base/node / ACPI: Enumerate node access class for 'struct access_coordinate' Dave Jiang
2024-02-15 16:24 ` Jonathan Cameron
2024-02-06 22:28 ` [PATCH v5 03/12] ACPI: HMAT: Introduce 2 levels of generic port access class Dave Jiang
2024-02-15 16:44 ` Jonathan Cameron [this message]
2024-02-06 22:28 ` [PATCH v5 04/12] ACPI: HMAT / cxl: Add retrieval of generic port coordinates for both access classes Dave Jiang
2024-02-15 16:46 ` Jonathan Cameron
2024-02-06 22:28 ` [PATCH v5 05/12] cxl: Split out combine_coordinates() for common shared usage Dave Jiang
2024-02-15 16:51 ` Jonathan Cameron
2024-02-16 21:28 ` Dave Jiang
2024-02-06 22:28 ` [PATCH v5 06/12] cxl: Split out host bridge access coordinates Dave Jiang
2024-02-15 16:56 ` Jonathan Cameron
2024-02-06 22:28 ` [PATCH v5 07/12] cxl: Move QoS class to be calculated from the nearest CPU Dave Jiang
2024-02-15 16:57 ` Jonathan Cameron
2024-02-06 22:28 ` [PATCH v5 08/12] cxl: Set cxlmd->endpoint before adding port device Dave Jiang
2024-02-15 17:01 ` Jonathan Cameron
2024-02-06 22:28 ` [PATCH v5 09/12] cxl/region: Calculate performance data for a region Dave Jiang
2024-02-06 22:28 ` [PATCH v5 10/12] cxl/region: Add sysfs attribute for locality attributes of CXL regions Dave Jiang
2024-02-15 17:08 ` Jonathan Cameron
2024-02-06 22:28 ` [PATCH v5 11/12] cxl/region: Add memory hotplug notifier for cxl region Dave Jiang
2024-02-15 17:16 ` Jonathan Cameron
2024-02-06 22:28 ` [PATCH v5 12/12] cxl/region: Deal with numa nodes not enumarated by SRAT Dave Jiang
2024-02-15 17:24 ` Jonathan Cameron
2024-02-20 20:47 ` Dave Jiang
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