From: Dave Jiang <dave.jiang@intel.com>
To: linux-cxl@vger.kernel.org, linux-acpi@vger.kernel.org
Cc: dan.j.williams@intel.com, ira.weiny@intel.com,
vishal.l.verma@intel.com, alison.schofield@intel.com,
Jonathan.Cameron@huawei.com, dave@stgolabs.net,
rafael@kernel.org, gregkh@linuxfoundation.org
Subject: [PATCH v7 05/12] cxl: Split out combine_coordinates() for common shared usage
Date: Fri, 8 Mar 2024 14:59:24 -0700 [thread overview]
Message-ID: <20240308220055.2172956-6-dave.jiang@intel.com> (raw)
In-Reply-To: <20240308220055.2172956-1-dave.jiang@intel.com>
Refactor the common code of combining coordinates in order to reduce code.
Create a new function cxl_cooordinates_combine() it combine two 'struct
access_coordinate'.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Tested-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
---
drivers/cxl/core/cdat.c | 32 +++++++++++++++++++++++---------
drivers/cxl/core/port.c | 18 ++----------------
drivers/cxl/cxl.h | 4 ++++
3 files changed, 29 insertions(+), 25 deletions(-)
diff --git a/drivers/cxl/core/cdat.c b/drivers/cxl/core/cdat.c
index 08fd0baea7a0..c1ede0ef9185 100644
--- a/drivers/cxl/core/cdat.c
+++ b/drivers/cxl/core/cdat.c
@@ -185,15 +185,7 @@ static int cxl_port_perf_data_calculate(struct cxl_port *port,
xa_for_each(dsmas_xa, index, dent) {
int qos_class;
- dent->coord.read_latency = dent->coord.read_latency +
- c.read_latency;
- dent->coord.write_latency = dent->coord.write_latency +
- c.write_latency;
- dent->coord.read_bandwidth = min_t(int, c.read_bandwidth,
- dent->coord.read_bandwidth);
- dent->coord.write_bandwidth = min_t(int, c.write_bandwidth,
- dent->coord.write_bandwidth);
-
+ cxl_coordinates_combine(&dent->coord, &dent->coord, &c);
dent->entries = 1;
rc = cxl_root->ops->qos_class(cxl_root, &dent->coord, 1,
&qos_class);
@@ -484,4 +476,26 @@ void cxl_switch_parse_cdat(struct cxl_port *port)
}
EXPORT_SYMBOL_NS_GPL(cxl_switch_parse_cdat, CXL);
+/**
+ * cxl_coordinates_combine - Combine the two input coordinates
+ *
+ * @out: Output coordinate of c1 and c2 combined
+ * @c1: input coordinates
+ * @c2: input coordinates
+ */
+void cxl_coordinates_combine(struct access_coordinate *out,
+ struct access_coordinate *c1,
+ struct access_coordinate *c2)
+{
+ if (c1->write_bandwidth && c2->write_bandwidth)
+ out->write_bandwidth = min(c1->write_bandwidth,
+ c2->write_bandwidth);
+ out->write_latency = c1->write_latency + c2->write_latency;
+
+ if (c1->read_bandwidth && c2->read_bandwidth)
+ out->read_bandwidth = min(c1->read_bandwidth,
+ c2->read_bandwidth);
+ out->read_latency = c1->read_latency + c2->read_latency;
+}
+
MODULE_IMPORT_NS(CXL);
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index 612bf7e1e847..af9458b2678c 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -2096,20 +2096,6 @@ bool schedule_cxl_memdev_detach(struct cxl_memdev *cxlmd)
}
EXPORT_SYMBOL_NS_GPL(schedule_cxl_memdev_detach, CXL);
-static void combine_coordinates(struct access_coordinate *c1,
- struct access_coordinate *c2)
-{
- if (c2->write_bandwidth)
- c1->write_bandwidth = min(c1->write_bandwidth,
- c2->write_bandwidth);
- c1->write_latency += c2->write_latency;
-
- if (c2->read_bandwidth)
- c1->read_bandwidth = min(c1->read_bandwidth,
- c2->read_bandwidth);
- c1->read_latency += c2->read_latency;
-}
-
/**
* cxl_endpoint_get_perf_coordinates - Retrieve performance numbers stored in dports
* of CXL path
@@ -2143,7 +2129,7 @@ int cxl_endpoint_get_perf_coordinates(struct cxl_port *port,
* nothing to gather.
*/
while (iter && !is_cxl_root(to_cxl_port(iter->dev.parent))) {
- combine_coordinates(&c, &dport->sw_coord);
+ cxl_coordinates_combine(&c, &c, &dport->sw_coord);
c.write_latency += dport->link_latency;
c.read_latency += dport->link_latency;
@@ -2152,7 +2138,7 @@ int cxl_endpoint_get_perf_coordinates(struct cxl_port *port,
}
/* Augment with the generic port (host bridge) perf data */
- combine_coordinates(&c, &dport->hb_coord[ACCESS_COORDINATE_LOCAL]);
+ cxl_coordinates_combine(&c, &c, &dport->hb_coord[ACCESS_COORDINATE_LOCAL]);
/* Get the calculated PCI paths bandwidth */
pdev = to_pci_dev(port->uport_dev->parent);
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index fe7448f2745e..fab2da4b1f04 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -882,6 +882,10 @@ int cxl_endpoint_get_perf_coordinates(struct cxl_port *port,
void cxl_memdev_update_perf(struct cxl_memdev *cxlmd);
+void cxl_coordinates_combine(struct access_coordinate *out,
+ struct access_coordinate *c1,
+ struct access_coordinate *c2);
+
/*
* Unit test builds overrides this to __weak, find the 'strong' version
* of these symbols in tools/testing/cxl/.
--
2.44.0
next prev parent reply other threads:[~2024-03-08 22:01 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-08 21:59 [PATCH v7 0/12] cxl: Add support to report region access coordinates to numa nodes Dave Jiang
2024-03-08 21:59 ` [PATCH v7 01/12] ACPI: HMAT: Remove register of memory node for generic target Dave Jiang
2024-03-08 21:59 ` [PATCH v7 02/12] base/node / ACPI: Enumerate node access class for 'struct access_coordinate' Dave Jiang
2024-03-08 21:59 ` [PATCH v7 03/12] ACPI: HMAT: Introduce 2 levels of generic port access class Dave Jiang
2024-03-08 21:59 ` [PATCH v7 04/12] ACPI: HMAT / cxl: Add retrieval of generic port coordinates for both access classes Dave Jiang
2024-03-08 21:59 ` Dave Jiang [this message]
2024-03-08 21:59 ` [PATCH v7 06/12] cxl: Split out host bridge access coordinates Dave Jiang
2024-03-08 21:59 ` [PATCH v7 07/12] cxl: Move QoS class to be calculated from the nearest CPU Dave Jiang
2024-03-08 21:59 ` [PATCH v7 08/12] cxl: Set cxlmd->endpoint before adding port device Dave Jiang
2024-03-08 21:59 ` [PATCH v7 09/12] cxl/region: Calculate performance data for a region Dave Jiang
2024-03-08 21:59 ` [PATCH v7 10/12] cxl/region: Add sysfs attribute for locality attributes of CXL regions Dave Jiang
2024-03-08 21:59 ` [PATCH v7 11/12] cxl/region: Add memory hotplug notifier for cxl region Dave Jiang
2024-03-12 20:03 ` Dan Williams
2024-03-08 21:59 ` [PATCH v7 12/12] cxl/region: Deal with numa nodes not enumerated by SRAT Dave Jiang
2024-03-12 21:41 ` Dan Williams
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