From: Sunil V L <sunilvl@ventanamicro.com>
To: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org,
acpica-devel@lists.linux.dev
Cc: "Catalin Marinas" <catalin.marinas@arm.com>,
"Will Deacon" <will@kernel.org>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Rafael J . Wysocki" <rafael@kernel.org>,
"Len Brown" <lenb@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Anup Patel" <anup@brainfault.org>,
"Thomas Gleixner" <tglx@linutronix.de>,
"Samuel Holland" <samuel.holland@sifive.com>,
"Robert Moore" <robert.moore@intel.com>,
"Conor Dooley" <conor.dooley@microchip.com>,
"Andrew Jones" <ajones@ventanamicro.com>,
"Andy Shevchenko" <andriy.shevchenko@linux.intel.com>,
"Marc Zyngier" <maz@kernel.org>,
"Atish Kumar Patra" <atishp@rivosinc.com>,
"Haibo1 Xu" <haibo1.xu@intel.com>,
"Björn Töpel" <bjorn@kernel.org>,
"Sunil V L" <sunilvl@ventanamicro.com>
Subject: [PATCH v6 14/17] irqchip/riscv-imsic-state: Create separate function for DT
Date: Sat, 1 Jun 2024 20:34:08 +0530 [thread overview]
Message-ID: <20240601150411.1929783-15-sunilvl@ventanamicro.com> (raw)
In-Reply-To: <20240601150411.1929783-1-sunilvl@ventanamicro.com>
While populating IMSIC global structure, many fields are initialized
using DT properties. Make the code which uses DT properties as separate
function so that it is easier to add ACPI support later. No
functionality added/changed.
Suggested-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
drivers/irqchip/irq-riscv-imsic-state.c | 97 ++++++++++++++-----------
1 file changed, 55 insertions(+), 42 deletions(-)
diff --git a/drivers/irqchip/irq-riscv-imsic-state.c b/drivers/irqchip/irq-riscv-imsic-state.c
index 5479f872e62b..f9e70832863a 100644
--- a/drivers/irqchip/irq-riscv-imsic-state.c
+++ b/drivers/irqchip/irq-riscv-imsic-state.c
@@ -510,6 +510,60 @@ static int __init imsic_matrix_init(void)
return 0;
}
+static int __init imsic_populate_global_dt(struct fwnode_handle *fwnode,
+ struct imsic_global_config *global,
+ u32 *nr_parent_irqs)
+{
+ int rc;
+
+ /* Find number of guest index bits in MSI address */
+ rc = of_property_read_u32(to_of_node(fwnode), "riscv,guest-index-bits",
+ &global->guest_index_bits);
+ if (rc)
+ global->guest_index_bits = 0;
+
+ /* Find number of HART index bits */
+ rc = of_property_read_u32(to_of_node(fwnode), "riscv,hart-index-bits",
+ &global->hart_index_bits);
+ if (rc) {
+ /* Assume default value */
+ global->hart_index_bits = __fls(*nr_parent_irqs);
+ if (BIT(global->hart_index_bits) < *nr_parent_irqs)
+ global->hart_index_bits++;
+ }
+
+ /* Find number of group index bits */
+ rc = of_property_read_u32(to_of_node(fwnode), "riscv,group-index-bits",
+ &global->group_index_bits);
+ if (rc)
+ global->group_index_bits = 0;
+
+ /*
+ * Find first bit position of group index.
+ * If not specified assumed the default APLIC-IMSIC configuration.
+ */
+ rc = of_property_read_u32(to_of_node(fwnode), "riscv,group-index-shift",
+ &global->group_index_shift);
+ if (rc)
+ global->group_index_shift = IMSIC_MMIO_PAGE_SHIFT * 2;
+
+ /* Find number of interrupt identities */
+ rc = of_property_read_u32(to_of_node(fwnode), "riscv,num-ids",
+ &global->nr_ids);
+ if (rc) {
+ pr_err("%pfwP: number of interrupt identities not found\n", fwnode);
+ return rc;
+ }
+
+ /* Find number of guest interrupt identities */
+ rc = of_property_read_u32(to_of_node(fwnode), "riscv,num-guest-ids",
+ &global->nr_guest_ids);
+ if (rc)
+ global->nr_guest_ids = global->nr_ids;
+
+ return 0;
+}
+
static int __init imsic_get_parent_hartid(struct fwnode_handle *fwnode,
u32 index, unsigned long *hartid)
{
@@ -578,50 +632,9 @@ static int __init imsic_parse_fwnode(struct fwnode_handle *fwnode,
return -EINVAL;
}
- /* Find number of guest index bits in MSI address */
- rc = of_property_read_u32(to_of_node(fwnode), "riscv,guest-index-bits",
- &global->guest_index_bits);
+ rc = imsic_populate_global_dt(fwnode, global, nr_parent_irqs);
if (rc)
- global->guest_index_bits = 0;
-
- /* Find number of HART index bits */
- rc = of_property_read_u32(to_of_node(fwnode), "riscv,hart-index-bits",
- &global->hart_index_bits);
- if (rc) {
- /* Assume default value */
- global->hart_index_bits = __fls(*nr_parent_irqs);
- if (BIT(global->hart_index_bits) < *nr_parent_irqs)
- global->hart_index_bits++;
- }
-
- /* Find number of group index bits */
- rc = of_property_read_u32(to_of_node(fwnode), "riscv,group-index-bits",
- &global->group_index_bits);
- if (rc)
- global->group_index_bits = 0;
-
- /*
- * Find first bit position of group index.
- * If not specified assumed the default APLIC-IMSIC configuration.
- */
- rc = of_property_read_u32(to_of_node(fwnode), "riscv,group-index-shift",
- &global->group_index_shift);
- if (rc)
- global->group_index_shift = IMSIC_MMIO_PAGE_SHIFT * 2;
-
- /* Find number of interrupt identities */
- rc = of_property_read_u32(to_of_node(fwnode), "riscv,num-ids",
- &global->nr_ids);
- if (rc) {
- pr_err("%pfwP: number of interrupt identities not found\n", fwnode);
return rc;
- }
-
- /* Find number of guest interrupt identities */
- rc = of_property_read_u32(to_of_node(fwnode), "riscv,num-guest-ids",
- &global->nr_guest_ids);
- if (rc)
- global->nr_guest_ids = global->nr_ids;
/* Sanity check guest index bits */
i = BITS_PER_LONG - IMSIC_MMIO_PAGE_SHIFT;
--
2.40.1
next prev parent reply other threads:[~2024-06-01 15:06 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-01 15:03 [PATCH v6 00/17] RISC-V: ACPI: Add external interrupt controller support Sunil V L
2024-06-01 15:03 ` [PATCH v6 01/17] arm64: PCI: Migrate ACPI related functions to pci-acpi.c Sunil V L
2024-06-01 15:03 ` [PATCH v6 02/17] ACPI: scan: Add a weak function to reorder the IRQCHIP probe Sunil V L
2024-06-01 15:03 ` [PATCH v6 03/17] ACPI: bus: Add acpi_riscv_init function Sunil V L
2024-06-01 15:03 ` [PATCH v6 04/17] ACPI: scan: Refactor dependency creation Sunil V L
2024-06-01 15:03 ` [PATCH v6 05/17] ACPI: scan: Add RISC-V interrupt controllers to honor list Sunil V L
2024-06-01 15:04 ` [PATCH v6 06/17] ACPI: scan: Define weak function to populate dependencies Sunil V L
2024-06-01 15:04 ` [PATCH v6 07/17] ACPI: bus: Add RINTC IRQ model for RISC-V Sunil V L
2024-06-01 15:04 ` [PATCH v6 08/17] ACPI: pci_link: Clear the dependencies after probe Sunil V L
2024-06-01 15:04 ` [PATCH v6 09/17] ACPI: RISC-V: Implement PCI related functionality Sunil V L
2024-06-01 15:04 ` [PATCH v6 10/17] ACPI: RISC-V: Implement function to reorder irqchip probe entries Sunil V L
2024-06-06 22:07 ` Bjorn Helgaas
2024-07-10 13:55 ` Sunil V L
2024-06-01 15:04 ` [PATCH v6 11/17] ACPI: RISC-V: Initialize GSI mapping structures Sunil V L
2024-06-06 22:32 ` Bjorn Helgaas
2024-07-10 10:45 ` Lorenzo Pieralisi
2024-07-10 13:42 ` Sunil V L
2024-06-01 15:04 ` [PATCH v6 12/17] ACPI: RISC-V: Implement function to add implicit dependencies Sunil V L
2024-06-01 15:04 ` [PATCH v6 13/17] irqchip/riscv-intc: Add ACPI support for AIA Sunil V L
2024-06-01 15:04 ` Sunil V L [this message]
2024-06-01 15:04 ` [PATCH v6 15/17] irqchip/riscv-imsic: Add ACPI support Sunil V L
2024-06-01 15:04 ` [PATCH v6 16/17] irqchip/riscv-aplic: " Sunil V L
2024-06-01 15:04 ` [PATCH v6 17/17] irqchip/sifive-plic: " Sunil V L
2024-06-25 7:25 ` [PATCH v6 00/17] RISC-V: ACPI: Add external interrupt controller support Thomas Gleixner
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20240601150411.1929783-15-sunilvl@ventanamicro.com \
--to=sunilvl@ventanamicro.com \
--cc=acpica-devel@lists.linux.dev \
--cc=ajones@ventanamicro.com \
--cc=andriy.shevchenko@linux.intel.com \
--cc=anup@brainfault.org \
--cc=aou@eecs.berkeley.edu \
--cc=atishp@rivosinc.com \
--cc=bhelgaas@google.com \
--cc=bjorn@kernel.org \
--cc=catalin.marinas@arm.com \
--cc=conor.dooley@microchip.com \
--cc=haibo1.xu@intel.com \
--cc=lenb@kernel.org \
--cc=linux-acpi@vger.kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=maz@kernel.org \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=rafael@kernel.org \
--cc=robert.moore@intel.com \
--cc=samuel.holland@sifive.com \
--cc=tglx@linutronix.de \
--cc=will@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox