From: Bjorn Helgaas <helgaas@kernel.org>
To: Sunil V L <sunilvl@ventanamicro.com>
Cc: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org,
acpica-devel@lists.linux.dev,
"Catalin Marinas" <catalin.marinas@arm.com>,
"Will Deacon" <will@kernel.org>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Rafael J . Wysocki" <rafael@kernel.org>,
"Len Brown" <lenb@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Anup Patel" <anup@brainfault.org>,
"Thomas Gleixner" <tglx@linutronix.de>,
"Samuel Holland" <samuel.holland@sifive.com>,
"Robert Moore" <robert.moore@intel.com>,
"Conor Dooley" <conor.dooley@microchip.com>,
"Andrew Jones" <ajones@ventanamicro.com>,
"Andy Shevchenko" <andriy.shevchenko@linux.intel.com>,
"Marc Zyngier" <maz@kernel.org>,
"Atish Kumar Patra" <atishp@rivosinc.com>,
"Haibo1 Xu" <haibo1.xu@intel.com>,
"Björn Töpel" <bjorn@kernel.org>
Subject: Re: [PATCH v6 10/17] ACPI: RISC-V: Implement function to reorder irqchip probe entries
Date: Thu, 6 Jun 2024 17:07:43 -0500 [thread overview]
Message-ID: <20240606220743.GA821335@bhelgaas> (raw)
In-Reply-To: <20240601150411.1929783-11-sunilvl@ventanamicro.com>
On Sat, Jun 01, 2024 at 08:34:04PM +0530, Sunil V L wrote:
> ACPI MADT entries for interrupt controllers don't have a way to describe
> the hierarchy. However, the hierarchy is known to the architecture and
> on RISC-V platforms, the MADT sub table types are ordered in the
> incremental order from the root controller which is RINTC. So, add
> architecture function for RISC-V to reorder the interrupt controller
> probing as per the hierarchy as below.
Is this ordering requirement documented anywhere? I don't see it in
the RISC-V ECRs to the ACPI r6.5 spec.
I guess the implication is that you need to process MADT structures in
order of ascending acpi_madt_type:
ACPI_MADT_TYPE_RINTC = 24,
ACPI_MADT_TYPE_IMSIC = 25,
ACPI_MADT_TYPE_APLIC = 26,
ACPI_MADT_TYPE_PLIC = 27,
regardless of the order they appear in the MADT? I.e., process all
the RINTC structures (in order of appearance in MADT), followed by all
the IMSIC structures, then all the APLIC structures, etc?
> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> ---
> drivers/acpi/riscv/Makefile | 2 +-
> drivers/acpi/riscv/irq.c | 32 ++++++++++++++++++++++++++++++++
> 2 files changed, 33 insertions(+), 1 deletion(-)
> create mode 100644 drivers/acpi/riscv/irq.c
>
> diff --git a/drivers/acpi/riscv/Makefile b/drivers/acpi/riscv/Makefile
> index 877de00d1b50..a96fdf1e2cb8 100644
> --- a/drivers/acpi/riscv/Makefile
> +++ b/drivers/acpi/riscv/Makefile
> @@ -1,4 +1,4 @@
> # SPDX-License-Identifier: GPL-2.0-only
> -obj-y += rhct.o init.o
> +obj-y += rhct.o init.o irq.o
> obj-$(CONFIG_ACPI_PROCESSOR_IDLE) += cpuidle.o
> obj-$(CONFIG_ACPI_CPPC_LIB) += cppc.o
> diff --git a/drivers/acpi/riscv/irq.c b/drivers/acpi/riscv/irq.c
> new file mode 100644
> index 000000000000..f56e103a501f
> --- /dev/null
> +++ b/drivers/acpi/riscv/irq.c
> @@ -0,0 +1,32 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (C) 2023-2024, Ventana Micro Systems Inc
> + * Author: Sunil V L <sunilvl@ventanamicro.com>
> + *
Spurious blank line.
> + */
> +
> +#include <linux/acpi.h>
> +#include <linux/sort.h>
> +
> +static int irqchip_cmp_func(const void *in0, const void *in1)
> +{
> + struct acpi_probe_entry *elem0 = (struct acpi_probe_entry *)in0;
> + struct acpi_probe_entry *elem1 = (struct acpi_probe_entry *)in1;
> +
> + return (elem0->type > elem1->type) - (elem0->type < elem1->type);
> +}
> +
> +/*
> + * RISC-V irqchips in MADT of ACPI spec are defined in the same order how
> + * they should be probed. Since IRQCHIP_ACPI_DECLARE doesn't define any
> + * order, this arch function will reorder the probe functions as per the
> + * required order for the architecture.
But this comment seems to contradict the commit log. This comment
says you should process MADT structures in the order they appear in
the MADT. But if that were the case, you wouldn't need to sort
anything.
Maybe "defined in the order they should be probed" means "in order of
increasing Interrupt Controller structure type value"?
> + */
> +void arch_sort_irqchip_probe(struct acpi_probe_entry *ap_head, int nr)
> +{
> + struct acpi_probe_entry *ape = ap_head;
> +
> + if (nr == 1 || !ACPI_COMPARE_NAMESEG(ACPI_SIG_MADT, ape->id))
> + return;
> + sort(ape, nr, sizeof(*ape), irqchip_cmp_func, NULL);
> +}
> --
> 2.40.1
>
next prev parent reply other threads:[~2024-06-06 22:07 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-01 15:03 [PATCH v6 00/17] RISC-V: ACPI: Add external interrupt controller support Sunil V L
2024-06-01 15:03 ` [PATCH v6 01/17] arm64: PCI: Migrate ACPI related functions to pci-acpi.c Sunil V L
2024-06-01 15:03 ` [PATCH v6 02/17] ACPI: scan: Add a weak function to reorder the IRQCHIP probe Sunil V L
2024-06-01 15:03 ` [PATCH v6 03/17] ACPI: bus: Add acpi_riscv_init function Sunil V L
2024-06-01 15:03 ` [PATCH v6 04/17] ACPI: scan: Refactor dependency creation Sunil V L
2024-06-01 15:03 ` [PATCH v6 05/17] ACPI: scan: Add RISC-V interrupt controllers to honor list Sunil V L
2024-06-01 15:04 ` [PATCH v6 06/17] ACPI: scan: Define weak function to populate dependencies Sunil V L
2024-06-01 15:04 ` [PATCH v6 07/17] ACPI: bus: Add RINTC IRQ model for RISC-V Sunil V L
2024-06-01 15:04 ` [PATCH v6 08/17] ACPI: pci_link: Clear the dependencies after probe Sunil V L
2024-06-01 15:04 ` [PATCH v6 09/17] ACPI: RISC-V: Implement PCI related functionality Sunil V L
2024-06-01 15:04 ` [PATCH v6 10/17] ACPI: RISC-V: Implement function to reorder irqchip probe entries Sunil V L
2024-06-06 22:07 ` Bjorn Helgaas [this message]
2024-07-10 13:55 ` Sunil V L
2024-06-01 15:04 ` [PATCH v6 11/17] ACPI: RISC-V: Initialize GSI mapping structures Sunil V L
2024-06-06 22:32 ` Bjorn Helgaas
2024-07-10 10:45 ` Lorenzo Pieralisi
2024-07-10 13:42 ` Sunil V L
2024-06-01 15:04 ` [PATCH v6 12/17] ACPI: RISC-V: Implement function to add implicit dependencies Sunil V L
2024-06-01 15:04 ` [PATCH v6 13/17] irqchip/riscv-intc: Add ACPI support for AIA Sunil V L
2024-06-01 15:04 ` [PATCH v6 14/17] irqchip/riscv-imsic-state: Create separate function for DT Sunil V L
2024-06-01 15:04 ` [PATCH v6 15/17] irqchip/riscv-imsic: Add ACPI support Sunil V L
2024-06-01 15:04 ` [PATCH v6 16/17] irqchip/riscv-aplic: " Sunil V L
2024-06-01 15:04 ` [PATCH v6 17/17] irqchip/sifive-plic: " Sunil V L
2024-06-25 7:25 ` [PATCH v6 00/17] RISC-V: ACPI: Add external interrupt controller support Thomas Gleixner
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