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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?UZgXvIMp90hPdnSeDkSuVY9fiFk0/fMJHSFtTlWOx2KjdZuK/rdZvW2H9dsH?= =?us-ascii?Q?qdKo32mJvbIAdx1rdMfPf6AXfin6N2RKlLxMFh0LTunn5mTyL1Q/U0Dcv8Co?= =?us-ascii?Q?TqeZa1Jqp/J7TzHMcztgNjqRGPsdjWhmjFyJ0jy9/bMhr8tNl+6ZmGMOoumh?= =?us-ascii?Q?g3jy5zwTlFEQpDWYbvajgX72ZGKeAQDNRsQoH+bgSsQ/YuASc71GDBPjH6Cu?= =?us-ascii?Q?Rz2NP3lbCYBnFndQLxox60gVCUT68TRqq2sSqKYk1f11X8Sx/0fhPps00Qom?= =?us-ascii?Q?u+gRKMszH1z7YAAjhDVrakHpjI0jDwi73i23P91KP5t9RTeTMfpbRx06I4hA?= =?us-ascii?Q?pLAEQGgSm3Xy+ORD0Tk2j8WAodTOxqI+Q5n3Rme8WR04efSjj3RCmLuq3ggp?= =?us-ascii?Q?vdrPGuMJLGAtltnIwzBCSmWhDFAxTkTKfRfq7ck2q3rvicHfbXu14Vh/WznQ?= =?us-ascii?Q?/pgaIfGFtIVTJvlZDQCPa8FhZAKbMvA5hSaw7Bczx0yBwWphfmvUC9VNX9AX?= =?us-ascii?Q?bXL431QjQ1mEtHRWrQik5x6teTkfDgXCthKWEO27H8j33xlzoN6/YgrHJQdD?= =?us-ascii?Q?ntfoArsWoWDTpZIAUeEHlLwGL+/4/00t/3BD9CBHPt0RJVpqvlE+ZBJbSiUB?= =?us-ascii?Q?xYDmSPghnMu2YDPqFOSE6sKSY/3MNkAtNRVy0//EV9v7VxraAAWcsQBfxn+3?= =?us-ascii?Q?gitWkURgLPOpRi0fmoVUWS4fBolkm7tbFeIb1YFphFDGC40T7jBVE/hbla1j?= =?us-ascii?Q?NXVl8ApBHhp8u8mtHtQ4Q5L1xouqwjb5c1FDAv2qHzoCaQXn5YnuXStTwIgi?= =?us-ascii?Q?/idldsK+cj74/XQKGLsU0e/YmgKEN4KFAm5h6PdlB+8POfykzdRElvlP/uMi?= =?us-ascii?Q?3SD5d/DEoEwicfAUFUCJEx2oLelGLBfbK8wX2bka+ecVpiaWjHQE9cWJZPtO?= =?us-ascii?Q?jBkYhC3a6p1sxTm+Hnu/lfk6f1yyopqyU/kX3gjY020QZBbBb7/nc/MsGHsj?= =?us-ascii?Q?vKgdlaT4oQ68Q2GUByEVEglyjc5bSot2ELaiVQXF6MISF97GPb+zCz2TRDNg?= =?us-ascii?Q?fgdMpn/Svxs35y1kQbstHpdSrdRicg7IVbx4N49an/2KqBHDyiJ+lNcnSJ26?= =?us-ascii?Q?yTYbR59ikJyNd7X8faXiwzSnDm3uRhhdEzUm9SL/NzS0fFroEOsdOrQidDQ5?= =?us-ascii?Q?0YiLmsFn4IPtoq0465zWB+QWKg9awymsB1YXGCHJmNCwVNFrTphpyuHRrmp+?= =?us-ascii?Q?ng94+BfWj+94SBsXGfSrUceX+NYFVXFoAdL2UsNMIr/2E+zryxT4VrQPjjjR?= =?us-ascii?Q?v6jVYD6XYlTxm7NW6zH3ih3VMet2XabWIowpSbsHTT5I+ZQIwa8ABI9h3Hau?= =?us-ascii?Q?O+OYSaCbVZuR7qdQOWX6fbtyG9g4d9qpdt5agfk0ysSy7EdEyTbBOF4b57s6?= =?us-ascii?Q?lUxxA6zJsxqs04stcx7eyJDS+r8nxAPVaKs9x9whIXC4vghllbkFI/qJsyff?= =?us-ascii?Q?0ZcuBm0VIPTJ9ZesbX8Z9s2T+ibwKTcpvNWYNGY7H/eo3UY7N0ZVe4mU3uZC?= =?us-ascii?Q?pWZtZ+UF43r3iS2jLDx1HnBeyKF74r/ryzh/WDXq?= X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 78385656-0bbb-40b4-9652-08dca8021b2a X-MS-Exchange-CrossTenant-AuthSource: BN8PR12MB3108.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jul 2024 14:50:18.0978 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: /i1S8ySb7pXhSInBCiUX3ZGoDtxXl9oruQ7llIeY0uzvXYHhpWQimBayo9V1lliRmie8x45zzwl3bKZNOqTINg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7020 On Thu, Jul 18, 2024 at 02:24:05PM +0800, LeoLiu-oc wrote: > From: LeoLiuoc > > Call the func pci_acpi_program_hest_aer_params() for every PCIe device, > the purpose of this function is to extract register value from HEST PCIe > AER structures and program them into AER Capabilities. This function > applies to all hardware platforms that has a PCI Express AER structure > in HEST. > > Signed-off-by: LeoLiuoc > --- > drivers/pci/pci-acpi.c | 101 +++++++++++++++++++++++++++++++++++++++++ > drivers/pci/pci.h | 9 ++++ > drivers/pci/probe.c | 1 + > 3 files changed, 111 insertions(+) > > diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c > index 004575091596..b522e8b226b8 100644 > --- a/drivers/pci/pci-acpi.c > +++ b/drivers/pci/pci-acpi.c > @@ -18,6 +18,7 @@ > #include > #include > #include > +#include > #include "pci.h" > > /* > @@ -783,6 +784,106 @@ int pci_acpi_program_hp_params(struct pci_dev *dev) > return -ENODEV; > } > > +#ifdef CONFIG_ACPI_APEI > +/* > + * program_hest_aer_common() - configure AER common registers for Root Ports, > + * Endpoints and PCIe to PCI/PCI-X bridges > + */ > +static void program_hest_aer_common(struct acpi_hest_aer_common aer_common, struct pci_dev *dev, > + int pos) > +{ > + u32 uncor_mask; > + u32 uncor_severity; > + u32 cor_mask; > + u32 adv_cap; > + > + uncor_mask = aer_common.uncorrectable_mask; > + uncor_severity = aer_common.uncorrectable_severity; > + cor_mask = aer_common.correctable_mask; > + adv_cap = aer_common.advanced_capabilities; > + > + pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, uncor_mask); > + pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, uncor_severity); > + pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, cor_mask); > + pci_write_config_dword(dev, pos + PCI_ERR_CAP, adv_cap); > +} > + > +static void program_hest_aer_root(struct acpi_hest_aer_root *aer_root, struct pci_dev *dev, int pos) > +{ > + u32 root_err_cmd; > + > + root_err_cmd = aer_root->root_error_command; > + > + pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, root_err_cmd); > +} > + > +static void program_hest_aer_bridge(struct acpi_hest_aer_bridge *hest_aer_bridge, > + struct pci_dev *dev, int pos) > +{ > + u32 uncor_mask2; > + u32 uncor_severity2; > + u32 adv_cap2; > + > + uncor_mask2 = hest_aer_bridge->uncorrectable_mask2; > + uncor_severity2 = hest_aer_bridge->uncorrectable_severity2; > + adv_cap2 = hest_aer_bridge->advanced_capabilities2; > + > + pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK2, uncor_mask2); > + pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER2, uncor_severity2); > + pci_write_config_dword(dev, pos + PCI_ERR_CAP2, adv_cap2); > +} > + > +static void program_hest_aer_params(struct hest_parse_aer_info info) > +{ > + struct pci_dev *dev; > + int port_type; > + int pos; > + struct acpi_hest_aer_root *hest_aer_root; > + struct acpi_hest_aer *hest_aer_endpoint; > + struct acpi_hest_aer_bridge *hest_aer_bridge; > + > + dev = info.pci_dev; > + port_type = pci_pcie_type(dev); > + pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); > + if (!pos) > + return; > + > + switch (port_type) { > + case PCI_EXP_TYPE_ROOT_PORT: > + hest_aer_root = info.hest_aer_root_port; > + program_hest_aer_common(hest_aer_root->aer, dev, pos); > + program_hest_aer_root(hest_aer_root, dev, pos); > + break; > + case PCI_EXP_TYPE_ENDPOINT: > + hest_aer_endpoint = info.hest_aer_endpoint; > + program_hest_aer_common(hest_aer_endpoint->aer, dev, pos); > + break; > + case PCI_EXP_TYPE_PCI_BRIDGE: > + hest_aer_bridge = info.hest_aer_bridge; > + program_hest_aer_common(hest_aer_bridge->aer, dev, pos); > + program_hest_aer_bridge(hest_aer_bridge, dev, pos); > + break; > + default: > + break; > + } > +} > + > +int pci_acpi_program_hest_aer_params(struct pci_dev *dev) > +{ > + struct hest_parse_aer_info info = { > + .pci_dev = dev > + }; > + > + if (!pci_is_pcie(dev)) > + return -ENODEV; > + > + if (apei_hest_parse(hest_parse_pcie_aer, &info) == 1) > + program_hest_aer_params(info); > + > + return 0; > +} > +#endif > + > /** > * pciehp_is_native - Check whether a hotplug port is handled by the OS > * @bridge: Hotplug port to check > diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h > index fd44565c4756..03b5339f399f 100644 > --- a/drivers/pci/pci.h > +++ b/drivers/pci/pci.h > @@ -731,6 +731,15 @@ static inline void pci_save_aer_state(struct pci_dev *dev) { } > static inline void pci_restore_aer_state(struct pci_dev *dev) { } > #endif > > +#ifdef CONFIG_ACPI_APEI > +int pci_acpi_program_hest_aer_params(struct pci_dev *dev); > +#else > +static inline int pci_acpi_program_hest_aer_params(struct pci_dev *dev) > +{ > + return 0; > +} > +#endif > + > #ifdef CONFIG_ACPI > int pci_acpi_program_hp_params(struct pci_dev *dev); > extern const struct attribute_group pci_dev_acpi_attr_group; > diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c > index 4c367f13acdc..f7d80b2a9d1d 100644 > --- a/drivers/pci/probe.c > +++ b/drivers/pci/probe.c > @@ -2267,6 +2267,7 @@ static void pci_configure_device(struct pci_dev *dev) > pci_configure_serr(dev); > > pci_acpi_program_hp_params(dev); > + pci_acpi_program_hest_aer_params(dev); > } > > static void pci_release_capabilities(struct pci_dev *dev) > -- I don't see where this accounts for _OSC negotiation. The OS must be granted control of AER before accessing AER registers in general. Thanks, Yazen