Re: [RFC PATCH 0/6] acpi/hmat / cxl: Add exclusive caching enumeration and RAS support

[Jonathan Cameron <Jonathan.Cameron@Huawei.com>]

On Fri, 27 Sep 2024 07:16:52 -0700
Dave Jiang <dave.jiang@intel.com> wrote:

> Hi all,
> I'm looking for comments on the approach and the implementation of dealing with
> this exclusive caching configuration. I have concerns with the discovering and
> handling of I/O hole in the memory mapping and looking for suggestions on if
> there are better ways to do it. I will be taking a 4 weeks sabbatical starting
> next week and I apologize in advance in the delay on responses. Thank you in
> advance for reviewing the patches.
> 
> The MCE folks will be interested in patch 6/6 where MCE_PRIO_CXL is added.
> 
> 
> Certain systems provide an exclusive caching memory configurations where a
> 1:1 layout of DRAM and far memory (FR) such as CXL memory is utilized. In
(FM) at least that is what you use later.


> this configuration, the memory region is provided as a single memory region
> to the OS. For example such as below:
> 
>              128GB DRAM                         128GB CXL memory
> |------------------------------------|------------------------------------|

So this differs slightly from what I expected.  
The ACPI spec change I believe allows for the CXL memory to be be N times
bigger than the cache.

I'm not against only supporting 1:1, but I didn't immediately see code
to check for that and scream if it sees something different.

Also as I mention in one of the patches, I don't recall the ACPI stuff
giving an 'order' to the two types of memory.  Maybe I'm missing that
but in theory at least I think the code needs to be more flexible
(or renamed perhaps).

Jonathan