From: Anshuman Gupta <anshuman.gupta@intel.com>
To: intel-xe@lists.freedesktop.org, linux-acpi@vger.kernel.org,
linux-pci@vger.kernel.org
Cc: rafael@kernel.org, lenb@kernel.org, bhelgaas@google.com,
ilpo.jarvinen@linux.intel.com, lucas.demarchi@intel.com,
rodrigo.vivi@intel.com, badal.nilawar@intel.com,
kam.nasim@intel.com, Anshuman Gupta <anshuman.gupta@intel.com>
Subject: [RFC 2/6] drm/xe/vrsr: Detect vrsr capability
Date: Mon, 24 Feb 2025 22:18:45 +0530 [thread overview]
Message-ID: <20250224164849.3746751-3-anshuman.gupta@intel.com> (raw)
In-Reply-To: <20250224164849.3746751-1-anshuman.gupta@intel.com>
Detect VRAM Self Refresh(vrsr) Capability.
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/xe/regs/xe_regs.h | 3 +++
drivers/gpu/drm/xe/xe_device_types.h | 4 ++++
drivers/gpu/drm/xe/xe_pm.c | 27 +++++++++++++++++++++++++++
3 files changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe_regs.h
index 6cf282618836..21563e9d958b 100644
--- a/drivers/gpu/drm/xe/regs/xe_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_regs.h
@@ -57,6 +57,9 @@
#define MTL_MPE_FREQUENCY XE_REG(0x13802c)
#define MTL_RPE_MASK REG_GENMASK(8, 0)
+#define VRAM_CAPABILITY XE_REG(0x138144)
+#define VRAM_SUPPORTED REG_BIT(0)
+
#define VF_CAP_REG XE_REG(0x1901f8, XE_REG_OPTION_VF)
#define VF_CAP REG_BIT(0)
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 4656305dd45a..c2ab2c91c968 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -490,6 +490,9 @@ struct xe_device {
/** @d3cold.allowed: Indicates if d3cold is a valid device state */
bool allowed;
+ /** @d3cold.vrsr_capable: Indicates if d3cold VRAM Self Refresh is supported */
+ bool vrsr_capable;
+
/**
* @d3cold.vram_threshold:
*
@@ -500,6 +503,7 @@ struct xe_device {
* Default threshold value is 300mb.
*/
u32 vram_threshold;
+
/** @d3cold.lock: protect vram_threshold */
struct mutex lock;
} d3cold;
diff --git a/drivers/gpu/drm/xe/xe_pm.c b/drivers/gpu/drm/xe/xe_pm.c
index 12200be7b43d..dead236355d8 100644
--- a/drivers/gpu/drm/xe/xe_pm.c
+++ b/drivers/gpu/drm/xe/xe_pm.c
@@ -17,12 +17,15 @@
#include "xe_bo_evict.h"
#include "xe_device.h"
#include "xe_device_sysfs.h"
+#include "xe_force_wake.h"
#include "xe_ggtt.h"
#include "xe_gt.h"
#include "xe_guc.h"
#include "xe_irq.h"
+#include "xe_mmio.h"
#include "xe_pcode.h"
#include "xe_pxp.h"
+#include "regs/xe_regs.h"
#include "xe_trace.h"
#include "xe_wa.h"
@@ -236,6 +239,28 @@ static bool xe_pm_pci_d3cold_capable(struct xe_device *xe)
return true;
}
+static bool xe_pm_vrsr_capable(struct xe_device *xe)
+{
+ struct xe_mmio *mmio = xe_root_tile_mmio(xe);
+ unsigned int fw_ref;
+ struct xe_gt *gt;
+ u32 val;
+
+ gt = xe_root_mmio_gt(xe);
+
+ if (!xe->info.probe_display)
+ return false;
+
+ fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL);
+ if (!fw_ref)
+ return false;
+
+ val = xe_mmio_read32(mmio, VRAM_CAPABILITY);
+ xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL);
+
+ return val & VRAM_SUPPORTED;
+}
+
static void xe_pm_runtime_init(struct xe_device *xe)
{
struct device *dev = xe->drm.dev;
@@ -303,6 +328,8 @@ int xe_pm_init(struct xe_device *xe)
err = xe_pm_set_vram_threshold(xe, DEFAULT_VRAM_THRESHOLD);
if (err)
return err;
+
+ xe->d3cold.vrsr_capable = xe_pm_vrsr_capable(xe);
}
xe_pm_runtime_init(xe);
--
2.34.1
next prev parent reply other threads:[~2025-02-24 16:50 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-24 16:48 [RFC 0/6] VRAM Self Refresh Anshuman Gupta
2025-02-24 16:48 ` [RFC 1/6] PCI/ACPI: Implement PCI FW _DSM method Anshuman Gupta
2025-02-24 19:40 ` Bjorn Helgaas
2025-02-25 18:25 ` Gupta, Anshuman
2025-02-25 20:30 ` Bjorn Helgaas
2025-02-24 16:48 ` Anshuman Gupta [this message]
2025-03-07 21:50 ` [RFC 2/6] drm/xe/vrsr: Detect vrsr capability Rodrigo Vivi
2025-02-24 16:48 ` [RFC 3/6] drm/xe/vrsr: Apis to init and enable VRSR feature Anshuman Gupta
2025-02-24 19:43 ` Bjorn Helgaas
2025-03-10 17:23 ` Rodrigo Vivi
2025-02-24 16:48 ` [RFC 4/6] drm/xe/vrsr: Refactor d3cold.allowed to a enum Anshuman Gupta
2025-03-10 17:28 ` Rodrigo Vivi
2025-04-01 5:24 ` Poosa, Karthik
2025-02-24 16:48 ` [RFC 5/6] drm/xe/pm: D3Cold target state Anshuman Gupta
2025-02-24 19:45 ` Bjorn Helgaas
2025-02-25 17:49 ` Ville Syrjälä
2025-02-25 18:00 ` Gupta, Anshuman
2025-02-25 18:44 ` Ville Syrjälä
2025-02-24 16:48 ` [RFC 6/6] drm/xe/vrsr: Enable VRSR Anshuman Gupta
2025-04-01 5:19 ` [RFC,6/6] " Poosa, Karthik
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20250224164849.3746751-3-anshuman.gupta@intel.com \
--to=anshuman.gupta@intel.com \
--cc=badal.nilawar@intel.com \
--cc=bhelgaas@google.com \
--cc=ilpo.jarvinen@linux.intel.com \
--cc=intel-xe@lists.freedesktop.org \
--cc=kam.nasim@intel.com \
--cc=lenb@kernel.org \
--cc=linux-acpi@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=lucas.demarchi@intel.com \
--cc=rafael@kernel.org \
--cc=rodrigo.vivi@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).