Re: [PATCH] ACPI/PPTT: fix off-by-one error

Rafael J. Wysocki
2025-05-07T12:35:38Z

On Wed, May 7, 2025 at 2:31 PM Sudeep Holla <sudeep.holla@arm.com> wrote:
>
> On Wed, May 07, 2025 at 11:56:48AM +0000, Heyne, Maximilian wrote:
> > On Wed, May 07, 2025 at 12:52:18PM +0100, Sudeep Holla wrote:
> > >
> > > Just to understand, this node is absolutely processor node with no
> > > private resources ? I find it hard to trust this as most of the CPUs
> > > do have L1 I&D caches. If they were present the table can't abruptly end
> > > like this.
> >
> > Yes looks like it. In our case the ACPI subtable has length 0x14 which is
> > exactly sizeof(acpi_pptt_processor).
> >
>
> OK, this seem like it is emulated platform with no private resources as
> it is specified in the other similar patch clearly(QEMU/VM). So this
> doesn't match real platforms. Your PPTT is wrong if it is real hardware
> platform as you must have private resources.
>
> Anyways if we allow emulation to present CPUs without private resources
> we may have to consider allowing this as the computed pointer will match
> the table end.
>
> Rafael,
>
> If it is OK for QEMU to present cacheless CPUs, then we need to allow
> this logic. What do you think ?

I don't see why QEMU would be disallowed to do so.