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From: Ben Cheatham <Benjamin.Cheatham@amd.com>
To: <linux-cxl@vger.kernel.org>, <linux-pci@vger.kernel.org>,
	<linux-acpi@vger.kernel.org>
Cc: Ben Cheatham <Benjamin.Cheatham@amd.com>
Subject: [PATCH 14/16] ACPI: Add CXL isolation _OSC fields
Date: Wed, 30 Jul 2025 16:47:16 -0500	[thread overview]
Message-ID: <20250730214718.10679-15-Benjamin.Cheatham@amd.com> (raw)
In-Reply-To: <20250730214718.10679-1-Benjamin.Cheatham@amd.com>

Add CXL Timeout and Isolation _OSC support and control fields, as
defined in the ECN at the link below. The ECN contents are expected to
appear in the CXL 4.0 specification. The link is only accessible to CXL
SSWG members, so a brief overview is provided here:

The ECN adds several fields to the CXL _OSC method (CXL 3.2 9.18.2)
for the purpose of reserving CXL isolation features for the platform
firmware's use. The fields introduced for kernel support reserve
toggling the CXL.mem isolation enable bit in the isolation control
register (CXL 3.2 8.2.4.24.2) and how the host is notified isolation has
occurred.

These fields will be used by the CXL driver to enable CXL isolation
according to the result of the handshake. Descriptions of these fields
are included in the commit messages of the commits where they are used.

Link: https://members.computeexpresslink.org/wg/software_systems/document/3118
Signed-off-by: Ben Cheatham <Benjamin.Cheatham@amd.com>
---
 drivers/acpi/pci_root.c | 9 +++++++++
 include/linux/acpi.h    | 3 +++
 2 files changed, 12 insertions(+)

diff --git a/drivers/acpi/pci_root.c b/drivers/acpi/pci_root.c
index 74ade4160314..33a922e160fc 100644
--- a/drivers/acpi/pci_root.c
+++ b/drivers/acpi/pci_root.c
@@ -145,10 +145,13 @@ static struct pci_osc_bit_struct cxl_osc_support_bit[] = {
 	{ OSC_CXL_2_0_PORT_DEV_REG_ACCESS_SUPPORT, "CXL20PortDevRegAccess" },
 	{ OSC_CXL_PROTOCOL_ERR_REPORTING_SUPPORT, "CXLProtocolErrorReporting" },
 	{ OSC_CXL_NATIVE_HP_SUPPORT, "CXLNativeHotPlug" },
+	{ OSC_CXL_TIMEOUT_ISOLATION_SUPPORT, "CXLTimeoutIsolation" },
 };
 
 static struct pci_osc_bit_struct cxl_osc_control_bit[] = {
 	{ OSC_CXL_ERROR_REPORTING_CONTROL, "CXLMemErrorReporting" },
+	{ OSC_CXL_MEM_ISOLATION_CONTROL, "CXLMemIsolation" },
+	{ OSC_CXL_ISOLATION_NOTIF_CONTROL, "CXLIsolationNotifications" },
 };
 
 static void decode_osc_bits(struct acpi_pci_root *root, char *msg, u32 word,
@@ -493,6 +496,8 @@ static u32 calculate_cxl_support(void)
 		support |= OSC_CXL_PROTOCOL_ERR_REPORTING_SUPPORT;
 	if (IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE))
 		support |= OSC_CXL_NATIVE_HP_SUPPORT;
+	if (IS_ENABLED(CONFIG_CXL_ISOLATION))
+		support |= OSC_CXL_TIMEOUT_ISOLATION_SUPPORT;
 
 	return support;
 }
@@ -535,6 +540,10 @@ static u32 calculate_cxl_control(void)
 	if (IS_ENABLED(CONFIG_MEMORY_FAILURE))
 		control |= OSC_CXL_ERROR_REPORTING_CONTROL;
 
+	if (IS_ENABLED(CONFIG_CXL_ISOLATION))
+		control |= (OSC_CXL_MEM_ISOLATION_CONTROL |
+			    OSC_CXL_ISOLATION_NOTIF_CONTROL);
+
 	return control;
 }
 
diff --git a/include/linux/acpi.h b/include/linux/acpi.h
index f102c0fe3431..f172182aa029 100644
--- a/include/linux/acpi.h
+++ b/include/linux/acpi.h
@@ -626,9 +626,12 @@ extern u32 osc_sb_native_usb4_control;
 #define OSC_CXL_2_0_PORT_DEV_REG_ACCESS_SUPPORT	0x00000002
 #define OSC_CXL_PROTOCOL_ERR_REPORTING_SUPPORT	0x00000004
 #define OSC_CXL_NATIVE_HP_SUPPORT		0x00000008
+#define OSC_CXL_TIMEOUT_ISOLATION_SUPPORT	0x00000010
 
 /* CXL _OSC: Capabilities DWORD 5: Control Field */
 #define OSC_CXL_ERROR_REPORTING_CONTROL		0x00000001
+#define OSC_CXL_MEM_ISOLATION_CONTROL		0x00000002
+#define OSC_CXL_ISOLATION_NOTIF_CONTROL		0x00000020
 
 static inline u32 acpi_osc_ctx_get_pci_control(struct acpi_osc_context *context)
 {
-- 
2.34.1


  parent reply	other threads:[~2025-07-30 21:50 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-07-30 21:47 [PATCH 00/16] CXL.mem error isolation support Ben Cheatham
2025-07-30 21:47 ` [PATCH 01/16] cxl/regs: Add cxl_unmap_component_regs() Ben Cheatham
2025-09-12 14:46   ` Jonathan Cameron
2025-09-17 17:26     ` Cheatham, Benjamin
2025-07-30 21:47 ` [PATCH 02/16] cxl/regs: Add CXL Isolation capability mapping Ben Cheatham
2025-09-12 14:47   ` Jonathan Cameron
2025-07-30 21:47 ` [PATCH 03/16] PCI: PCIe portdrv: Add CXL Isolation service driver Ben Cheatham
2025-09-12 15:14   ` Jonathan Cameron
2025-09-17 17:26     ` Cheatham, Benjamin
2025-07-30 21:47 ` [PATCH 04/16] PCI: PCIe portdrv: Allocate CXL isolation MSI/-X vector Ben Cheatham
2025-08-04 21:39   ` Bjorn Helgaas
2025-08-06 17:58     ` Cheatham, Benjamin
2025-07-30 21:47 ` [PATCH 05/16] PCI: PCIe portdrv: Add interface for getting CXL isolation IRQ Ben Cheatham
2025-07-31  5:59   ` Lukas Wunner
2025-07-31 13:13     ` Cheatham, Benjamin
2025-07-30 21:47 ` [PATCH 06/16] cxl/core: Enable CXL.mem isolation Ben Cheatham
2025-09-12 15:21   ` Jonathan Cameron
2025-09-17 17:26     ` Cheatham, Benjamin
2025-07-30 21:47 ` [PATCH 07/16] cxl/core: Set up isolation interrupts Ben Cheatham
2025-09-12 15:25   ` Jonathan Cameron
2025-09-17 17:27     ` Cheatham, Benjamin
2025-07-30 21:47 ` [PATCH 08/16] cxl/core: Enable CXL " Ben Cheatham
2025-07-30 21:47 ` [PATCH 09/16] cxl/core: Prevent onlining CXL memory behind isolated ports Ben Cheatham
2025-07-30 21:47 ` [PATCH 10/16] cxl/core: Enable CXL.mem timeout Ben Cheatham
2025-07-30 21:47 ` [PATCH 11/16] cxl/pci: Add isolation handler Ben Cheatham
2025-07-30 21:47 ` [PATCH 12/16] PCI: PCIe portdrv: Add cxl_isolation sysfs attributes Ben Cheatham
2025-09-12 15:33   ` Jonathan Cameron
2025-09-17 17:27     ` Cheatham, Benjamin
2025-07-30 21:47 ` [PATCH 13/16] cxl/core, PCI: PCIe portdrv: Add CXL timeout range programming Ben Cheatham
2025-08-04 21:39   ` Bjorn Helgaas
2025-08-06 17:58     ` Cheatham, Benjamin
2025-09-12 15:55   ` Jonathan Cameron
2025-09-17 17:27     ` Cheatham, Benjamin
2025-07-30 21:47 ` Ben Cheatham [this message]
2025-08-22 19:19   ` [PATCH 14/16] ACPI: Add CXL isolation _OSC fields Rafael J. Wysocki
2025-07-30 21:47 ` [PATCH 15/16] cxl/core, cxl/acpi: Enable CXL isolation based on _OSC handshake Ben Cheatham
2025-07-30 21:47 ` [PATCH 16/16] cxl/core, cxl/acpi: Add CXL isolation notify handler Ben Cheatham

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