From: Ben Cheatham <Benjamin.Cheatham@amd.com>
To: <linux-cxl@vger.kernel.org>, <linux-pci@vger.kernel.org>,
<linux-acpi@vger.kernel.org>
Cc: Ben Cheatham <Benjamin.Cheatham@amd.com>
Subject: [PATCH 01/16] cxl/regs: Add cxl_unmap_component_regs()
Date: Wed, 30 Jul 2025 16:47:03 -0500 [thread overview]
Message-ID: <20250730214718.10679-2-Benjamin.Cheatham@amd.com> (raw)
In-Reply-To: <20250730214718.10679-1-Benjamin.Cheatham@amd.com>
In order to allocate the MSI/-X interrupt for CXL error isolation the
PCIe portdrv driver needs to map the MMIO-space isolation capability
register that contains the interrupt vector. The CXL core already
provides a function to map registers in this space:
cxl_map_component_regs(). The mappings given this function are managed
by devres. If the isolation registers are left mapped by the PCIe
portdrv driver, the CXL driver will run into a devres conflict when it
goes to map the same registers during probe.
Add cxl_unmap_component_regs() to be called from the PCIe portdrv
driver. This function will unwind the devres allocations done by
cxl_map_component_regs(), which will allow the PCIe portdrv driver to
map the isolation capability register without conflicts.
Factor out the register mapping retrieval code in
cxl_map_component_regs() to be reused by cxl_map/unmap_component_regs().
Signed-off-by: Ben Cheatham <Benjamin.Cheatham@amd.com>
---
drivers/cxl/core/regs.c | 77 +++++++++++++++++++++++++++++++----------
drivers/cxl/cxl.h | 3 ++
2 files changed, 62 insertions(+), 18 deletions(-)
diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c
index b8e767a9571c..da8e668a3b70 100644
--- a/drivers/cxl/core/regs.c
+++ b/drivers/cxl/core/regs.c
@@ -201,40 +201,81 @@ void __iomem *devm_cxl_iomap_block(struct device *dev, resource_size_t addr,
}
EXPORT_SYMBOL_NS_GPL(devm_cxl_iomap_block, "CXL");
-int cxl_map_component_regs(const struct cxl_register_map *map,
+struct mapinfo {
+ const struct cxl_reg_map *rmap;
+ void __iomem **addr;
+};
+
+static int cxl_get_mapinfo(const struct cxl_register_map *map,
struct cxl_component_regs *regs,
- unsigned long map_mask)
+ unsigned long map_mask, struct mapinfo *info)
{
- struct device *host = map->host;
- struct mapinfo {
- const struct cxl_reg_map *rmap;
- void __iomem **addr;
- } mapinfo[] = {
+ struct mapinfo mapinfo[] = {
{ &map->component_map.hdm_decoder, ®s->hdm_decoder },
{ &map->component_map.ras, ®s->ras },
};
int i;
for (i = 0; i < ARRAY_SIZE(mapinfo); i++) {
- struct mapinfo *mi = &mapinfo[i];
- resource_size_t addr;
- resource_size_t length;
-
- if (!mi->rmap->valid)
+ if (!mapinfo[i].rmap->valid)
continue;
- if (!test_bit(mi->rmap->id, &map_mask))
+ if (!test_bit(mapinfo[i].rmap->id, &map_mask))
continue;
- addr = map->resource + mi->rmap->offset;
- length = mi->rmap->size;
- *(mi->addr) = devm_cxl_iomap_block(host, addr, length);
- if (!*(mi->addr))
- return -ENOMEM;
+
+ *info = mapinfo[i];
+ return 0;
}
+ return -ENXIO;
+}
+
+int cxl_map_component_regs(const struct cxl_register_map *map,
+ struct cxl_component_regs *regs,
+ unsigned long map_mask)
+{
+ struct device *host = map->host;
+ resource_size_t addr, length;
+ struct mapinfo mi;
+ int rc;
+
+ rc = cxl_get_mapinfo(map, regs, map_mask, &mi);
+ if (rc)
+ return rc;
+
+ addr = map->resource + mi.rmap->offset;
+ length = mi.rmap->size;
+ *mi.addr = devm_cxl_iomap_block(host, addr, length);
+ if (!(*mi.addr))
+ return -ENOMEM;
+
return 0;
}
EXPORT_SYMBOL_NS_GPL(cxl_map_component_regs, "CXL");
+int cxl_unmap_component_regs(const struct cxl_register_map *map,
+ struct cxl_component_regs *regs,
+ unsigned long map_mask)
+{
+ struct device *host = map->host;
+ resource_size_t addr, length;
+ struct mapinfo mi;
+ int rc;
+
+ rc = cxl_get_mapinfo(map, regs, map_mask, &mi);
+ if (rc)
+ return rc;
+
+ if (!(*mi.addr))
+ return 0;
+
+ addr = map->resource + mi.rmap->offset;
+ length = mi.rmap->size;
+
+ devm_iounmap(host, *mi.addr);
+ devm_release_mem_region(host, addr, length);
+ return 0;
+}
+
int cxl_map_device_regs(const struct cxl_register_map *map,
struct cxl_device_regs *regs)
{
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 51b7058387ef..a0fda305e25b 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -300,6 +300,9 @@ void cxl_probe_device_regs(struct device *dev, void __iomem *base,
int cxl_map_component_regs(const struct cxl_register_map *map,
struct cxl_component_regs *regs,
unsigned long map_mask);
+int cxl_unmap_component_regs(const struct cxl_register_map *map,
+ struct cxl_component_regs *regs,
+ unsigned long map_mask);
int cxl_map_device_regs(const struct cxl_register_map *map,
struct cxl_device_regs *regs);
int cxl_map_pmu_regs(struct cxl_register_map *map, struct cxl_pmu_regs *regs);
--
2.34.1
next prev parent reply other threads:[~2025-07-30 21:48 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-30 21:47 [PATCH 00/16] CXL.mem error isolation support Ben Cheatham
2025-07-30 21:47 ` Ben Cheatham [this message]
2025-09-12 14:46 ` [PATCH 01/16] cxl/regs: Add cxl_unmap_component_regs() Jonathan Cameron
2025-09-17 17:26 ` Cheatham, Benjamin
2025-07-30 21:47 ` [PATCH 02/16] cxl/regs: Add CXL Isolation capability mapping Ben Cheatham
2025-09-12 14:47 ` Jonathan Cameron
2025-07-30 21:47 ` [PATCH 03/16] PCI: PCIe portdrv: Add CXL Isolation service driver Ben Cheatham
2025-09-12 15:14 ` Jonathan Cameron
2025-09-17 17:26 ` Cheatham, Benjamin
2025-07-30 21:47 ` [PATCH 04/16] PCI: PCIe portdrv: Allocate CXL isolation MSI/-X vector Ben Cheatham
2025-08-04 21:39 ` Bjorn Helgaas
2025-08-06 17:58 ` Cheatham, Benjamin
2025-07-30 21:47 ` [PATCH 05/16] PCI: PCIe portdrv: Add interface for getting CXL isolation IRQ Ben Cheatham
2025-07-31 5:59 ` Lukas Wunner
2025-07-31 13:13 ` Cheatham, Benjamin
2025-07-30 21:47 ` [PATCH 06/16] cxl/core: Enable CXL.mem isolation Ben Cheatham
2025-09-12 15:21 ` Jonathan Cameron
2025-09-17 17:26 ` Cheatham, Benjamin
2025-07-30 21:47 ` [PATCH 07/16] cxl/core: Set up isolation interrupts Ben Cheatham
2025-09-12 15:25 ` Jonathan Cameron
2025-09-17 17:27 ` Cheatham, Benjamin
2025-07-30 21:47 ` [PATCH 08/16] cxl/core: Enable CXL " Ben Cheatham
2025-07-30 21:47 ` [PATCH 09/16] cxl/core: Prevent onlining CXL memory behind isolated ports Ben Cheatham
2025-07-30 21:47 ` [PATCH 10/16] cxl/core: Enable CXL.mem timeout Ben Cheatham
2025-07-30 21:47 ` [PATCH 11/16] cxl/pci: Add isolation handler Ben Cheatham
2025-07-30 21:47 ` [PATCH 12/16] PCI: PCIe portdrv: Add cxl_isolation sysfs attributes Ben Cheatham
2025-09-12 15:33 ` Jonathan Cameron
2025-09-17 17:27 ` Cheatham, Benjamin
2025-07-30 21:47 ` [PATCH 13/16] cxl/core, PCI: PCIe portdrv: Add CXL timeout range programming Ben Cheatham
2025-08-04 21:39 ` Bjorn Helgaas
2025-08-06 17:58 ` Cheatham, Benjamin
2025-09-12 15:55 ` Jonathan Cameron
2025-09-17 17:27 ` Cheatham, Benjamin
2025-07-30 21:47 ` [PATCH 14/16] ACPI: Add CXL isolation _OSC fields Ben Cheatham
2025-08-22 19:19 ` Rafael J. Wysocki
2025-07-30 21:47 ` [PATCH 15/16] cxl/core, cxl/acpi: Enable CXL isolation based on _OSC handshake Ben Cheatham
2025-07-30 21:47 ` [PATCH 16/16] cxl/core, cxl/acpi: Add CXL isolation notify handler Ben Cheatham
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