From: Yazen Ghannam <yazen.ghannam@amd.com>
To: <x86@kernel.org>, Tony Luck <tony.luck@intel.com>,
"Rafael J. Wysocki" <rafael@kernel.org>
Cc: <linux-kernel@vger.kernel.org>, <linux-edac@vger.kernel.org>,
<Smita.KoralahalliChannabasappa@amd.com>,
Qiuxu Zhuo <qiuxu.zhuo@intel.com>,
Nikolay Borisov <nik.borisov@suse.com>,
<linux-acpi@vger.kernel.org>,
"Yazen Ghannam" <yazen.ghannam@amd.com>
Subject: [PATCH v6 01/15] x86/mce: Set CR4.MCE last during init
Date: Mon, 8 Sep 2025 15:40:30 +0000 [thread overview]
Message-ID: <20250908-wip-mca-updates-v6-1-eef5d6c74b9c@amd.com> (raw)
In-Reply-To: <20250908-wip-mca-updates-v6-0-eef5d6c74b9c@amd.com>
Set the CR4.MCE bit as the last step during init. This brings the MCA
init flow closer to what is described in the x86 docs.
x86 docs:
AMD Intel
MCG_CTL
MCA_CONFIG MCG_EXT_CTL
MCi_CTL MCi_CTL
MCG_CTL
CR4.MCE CR4.MCE
Current Linux:
AMD Intel
CR4.MCE CR4.MCE
MCG_CTL MCG_CTL
MCA_CONFIG MCG_EXT_CTL
MCi_CTL MCi_CTL
Updated Linux:
AMD Intel
MCG_CTL MCG_CTL
MCA_CONFIG MCG_EXT_CTL
MCi_CTL MCi_CTL
CR4.MCE CR4.MCE
The new init flow will match Intel's docs, but there will still be a
mismatch for AMD regarding MCG_CTL. However, there is no known issue
with this ordering, so leave it for now.
Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
---
Notes:
Link:
https://lore.kernel.org/r/20250825-wip-mca-updates-v5-7-865768a2eef8@amd.com
v5->v6:
* Only move CR4.MCE programming.
* Update commit message to match the new change.
v4->v5:
* New in v5.
arch/x86/kernel/cpu/mce/core.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index 0326fbb83adc..9e31834b3542 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -1850,8 +1850,6 @@ static void __mcheck_cpu_init_generic(void)
{
u64 cap;
- cr4_set_bits(X86_CR4_MCE);
-
rdmsrq(MSR_IA32_MCG_CAP, cap);
if (cap & MCG_CTL_P)
wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
@@ -2276,6 +2274,7 @@ void mcheck_cpu_init(struct cpuinfo_x86 *c)
__mcheck_cpu_init_vendor(c);
__mcheck_cpu_init_prepare_banks();
__mcheck_cpu_setup_timer();
+ cr4_set_bits(X86_CR4_MCE);
}
/*
@@ -2443,6 +2442,7 @@ static void mce_syscore_resume(void)
__mcheck_cpu_init_generic();
__mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info));
__mcheck_cpu_init_prepare_banks();
+ cr4_set_bits(X86_CR4_MCE);
}
static struct syscore_ops mce_syscore_ops = {
@@ -2462,6 +2462,7 @@ static void mce_cpu_restart(void *data)
__mcheck_cpu_init_generic();
__mcheck_cpu_init_prepare_banks();
__mcheck_cpu_init_timer();
+ cr4_set_bits(X86_CR4_MCE);
}
/* Reinit MCEs after user configuration changes */
--
2.51.0
next prev parent reply other threads:[~2025-09-08 15:41 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-08 15:40 [PATCH v6 00/15] AMD MCA interrupts rework Yazen Ghannam
2025-09-08 15:40 ` Yazen Ghannam [this message]
2025-09-10 11:43 ` [PATCH v6 01/15] x86/mce: Set CR4.MCE last during init Nikolay Borisov
2025-09-08 15:40 ` [PATCH v6 02/15] x86/mce: Define BSP-only init Yazen Ghannam
2025-09-10 11:47 ` Nikolay Borisov
2025-09-10 13:53 ` Yazen Ghannam
2025-09-10 14:28 ` Nikolay Borisov
2025-09-10 17:23 ` Luck, Tony
2025-09-08 15:40 ` [PATCH v6 03/15] x86/mce: Define BSP-only SMCA init Yazen Ghannam
2025-09-10 11:48 ` Nikolay Borisov
2025-09-08 15:40 ` [PATCH v6 04/15] x86/mce: Do 'UNKNOWN' vendor check early Yazen Ghannam
2025-09-10 13:27 ` Nikolay Borisov
2025-09-08 15:40 ` [PATCH v6 05/15] x86/mce: Separate global and per-CPU quirks Yazen Ghannam
2025-09-10 13:29 ` Nikolay Borisov
2025-09-08 15:40 ` [PATCH v6 06/15] x86/mce: Move machine_check_poll() status checks to helper functions Yazen Ghannam
2025-09-10 15:09 ` Nikolay Borisov
2025-09-08 15:40 ` [PATCH v6 07/15] x86/mce: Add clear_bank() helper Yazen Ghannam
2025-09-10 15:22 ` Nikolay Borisov
2025-09-08 15:40 ` [PATCH v6 08/15] x86/mce: Unify AMD THR handler with MCA Polling Yazen Ghannam
2025-09-08 15:40 ` [PATCH v6 09/15] x86/mce: Unify AMD DFR " Yazen Ghannam
2025-09-08 15:40 ` [PATCH v6 10/15] x86/mce/amd: Enable interrupt vectors once per-CPU on SMCA systems Yazen Ghannam
2025-09-11 10:22 ` Nikolay Borisov
2025-09-11 15:53 ` Yazen Ghannam
2025-09-08 15:40 ` [PATCH v6 11/15] x86/mce/amd: Support SMCA Corrected Error Interrupt Yazen Ghannam
2025-09-08 15:40 ` [PATCH v6 12/15] x86/mce/amd: Remove redundant reset_block() Yazen Ghannam
2025-09-11 14:42 ` Nikolay Borisov
2025-09-11 16:11 ` Yazen Ghannam
2025-09-08 15:40 ` [PATCH v6 13/15] x86/mce/amd: Define threshold restart function for banks Yazen Ghannam
2025-09-11 14:49 ` Nikolay Borisov
2025-09-08 15:40 ` [PATCH v6 14/15] x86/mce: Handle AMD threshold interrupt storms Yazen Ghannam
2025-09-08 15:40 ` [PATCH v6 15/15] x86/mce: Save and use APEI corrected threshold limit Yazen Ghannam
2025-09-11 17:01 ` Nikolay Borisov
2025-09-15 17:33 ` Yazen Ghannam
2025-09-19 10:42 ` Nikolay Borisov
2025-09-22 13:58 ` Yazen Ghannam
2025-09-08 16:10 ` [PATCH v6 00/15] AMD MCA interrupts rework Luck, Tony
2025-09-09 13:36 ` Yazen Ghannam
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