From: Himanshu Chauhan <hchauhan@ventanamicro.com>
To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-acpi@vger.kernel.org, linux-efi@vger.kernel.org,
acpica-devel@lists.linux.dev
Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, lenb@kernel.org,
james.morse@arm.com, tony.luck@intel.com, ardb@kernel.org,
conor@kernel.org, cleger@rivosinc.com, robert.moore@intel.com,
sunilvl@ventanamicro.com, apatel@ventanamicro.com,
Himanshu Chauhan <hchauhan@ventanamicro.com>
Subject: [RFC PATCH v2 10/10] riscv: Enable APEI GHES driver in defconfig
Date: Wed, 29 Oct 2025 16:56:48 +0530 [thread overview]
Message-ID: <20251029112649.3811657-11-hchauhan@ventanamicro.com> (raw)
In-Reply-To: <20251029112649.3811657-1-hchauhan@ventanamicro.com>
The APEI GHES driver is very important for error handling on ACPI
based platforms so enable it in defconfig.
Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
---
arch/riscv/configs/defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index fc2725cbca18..3e62484e148f 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -44,6 +44,9 @@ CONFIG_ACPI_CPPC_CPUFREQ=m
CONFIG_VIRTUALIZATION=y
CONFIG_KVM=m
CONFIG_ACPI=y
+CONFIG_ACPI_APEI=y
+CONFIG_ACPI_APEI_GHES=y
+CONFIG_ACPI_APEI_ERST_DEBUG=y
CONFIG_JUMP_LABEL=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
--
2.43.0
prev parent reply other threads:[~2025-10-29 11:27 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-29 11:26 [RFC PATCH v2 00/10] Add RAS support for RISC-V architecture Himanshu Chauhan
2025-10-29 11:26 ` [RFC PATCH v2 01/10] riscv: Define ioremap_cache for RISC-V Himanshu Chauhan
2025-10-29 11:26 ` [RFC PATCH v2 02/10] riscv: Define arch_apei_get_mem_attribute " Himanshu Chauhan
2025-10-29 11:26 ` [RFC PATCH v2 03/10] acpi: Introduce SSE in HEST notification types Himanshu Chauhan
2025-11-05 8:33 ` Clément Léger
2025-10-29 11:26 ` [RFC PATCH v2 04/10] riscv: Add fixmap indices for GHES IRQ and SSE contexts Himanshu Chauhan
2025-11-05 8:41 ` Clément Léger
2025-10-29 11:26 ` [RFC PATCH v2 05/10] riscv: conditionally compile GHES NMI spool function Himanshu Chauhan
2025-10-29 11:26 ` [RFC PATCH v2 06/10] riscv: Add functions to register ghes having SSE notification Himanshu Chauhan
2025-11-05 10:33 ` Clément Léger
2025-10-29 11:26 ` [RFC PATCH v2 07/10] riscv: Add RISC-V entries in processor type and ISA strings Himanshu Chauhan
2025-10-29 11:26 ` [RFC PATCH v2 08/10] riscv: Introduce HEST SSE notification handlers Himanshu Chauhan
2025-10-29 11:26 ` [RFC PATCH v2 09/10] riscv: Select HAVE_ACPI_APEI required for RAS Himanshu Chauhan
2025-10-29 11:26 ` Himanshu Chauhan [this message]
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