From: Himanshu Chauhan <hchauhan@ventanamicro.com>
To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-acpi@vger.kernel.org, linux-efi@vger.kernel.org,
acpica-devel@lists.linux.dev
Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, lenb@kernel.org,
james.morse@arm.com, tony.luck@intel.com, ardb@kernel.org,
conor@kernel.org, cleger@rivosinc.com, robert.moore@intel.com,
sunilvl@ventanamicro.com, apatel@ventanamicro.com,
Himanshu Chauhan <hchauhan@ventanamicro.com>
Subject: [RFC PATCH v2 02/10] riscv: Define arch_apei_get_mem_attribute for RISC-V
Date: Wed, 29 Oct 2025 16:56:40 +0530 [thread overview]
Message-ID: <20251029112649.3811657-3-hchauhan@ventanamicro.com> (raw)
In-Reply-To: <20251029112649.3811657-1-hchauhan@ventanamicro.com>
ghes_map function uses arch_apei_get_mem_attribute to get the
protection bits for a given physical address. These protection
bits are then used to map the physical address.
Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
---
arch/riscv/include/asm/acpi.h | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/riscv/include/asm/acpi.h b/arch/riscv/include/asm/acpi.h
index 6e13695120bc..0c599452ef48 100644
--- a/arch/riscv/include/asm/acpi.h
+++ b/arch/riscv/include/asm/acpi.h
@@ -27,6 +27,26 @@ extern int acpi_disabled;
extern int acpi_noirq;
extern int acpi_pci_disabled;
+#ifdef CONFIG_ACPI_APEI
+/*
+ * acpi_disable_cmcff is used in drivers/acpi/apei/hest.c for disabling
+ * IA-32 Architecture Corrected Machine Check (CMC) Firmware-First mode
+ * with a kernel command line parameter "acpi=nocmcoff". But we don't
+ * have this IA-32 specific feature on ARM64, this definition is only
+ * for compatibility.
+ */
+#define acpi_disable_cmcff 1
+static inline pgprot_t arch_apei_get_mem_attribute(phys_addr_t addr)
+{
+ /*
+ * Until we have a way to look for EFI memory attributes.
+ */
+ return PAGE_KERNEL;
+}
+#else /* CONFIG_ACPI_APEI */
+#define acpi_disable_cmcff 0
+#endif /* !CONFIG_ACPI_APEI */
+
static inline void disable_acpi(void)
{
acpi_disabled = 1;
--
2.43.0
next prev parent reply other threads:[~2025-10-29 11:27 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-29 11:26 [RFC PATCH v2 00/10] Add RAS support for RISC-V architecture Himanshu Chauhan
2025-10-29 11:26 ` [RFC PATCH v2 01/10] riscv: Define ioremap_cache for RISC-V Himanshu Chauhan
2025-10-29 11:26 ` Himanshu Chauhan [this message]
2025-10-29 11:26 ` [RFC PATCH v2 03/10] acpi: Introduce SSE in HEST notification types Himanshu Chauhan
2025-11-05 8:33 ` Clément Léger
2025-10-29 11:26 ` [RFC PATCH v2 04/10] riscv: Add fixmap indices for GHES IRQ and SSE contexts Himanshu Chauhan
2025-11-05 8:41 ` Clément Léger
2025-10-29 11:26 ` [RFC PATCH v2 05/10] riscv: conditionally compile GHES NMI spool function Himanshu Chauhan
2025-10-29 11:26 ` [RFC PATCH v2 06/10] riscv: Add functions to register ghes having SSE notification Himanshu Chauhan
2025-11-05 10:33 ` Clément Léger
2025-10-29 11:26 ` [RFC PATCH v2 07/10] riscv: Add RISC-V entries in processor type and ISA strings Himanshu Chauhan
2025-10-29 11:26 ` [RFC PATCH v2 08/10] riscv: Introduce HEST SSE notification handlers Himanshu Chauhan
2025-10-29 11:26 ` [RFC PATCH v2 09/10] riscv: Select HAVE_ACPI_APEI required for RAS Himanshu Chauhan
2025-10-29 11:26 ` [RFC PATCH v2 10/10] riscv: Enable APEI GHES driver in defconfig Himanshu Chauhan
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