From: Himanshu Chauhan <hchauhan@ventanamicro.com>
To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-acpi@vger.kernel.org, linux-efi@vger.kernel.org,
acpica-devel@lists.linux.dev
Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, lenb@kernel.org,
james.morse@arm.com, tony.luck@intel.com, ardb@kernel.org,
conor@kernel.org, cleger@rivosinc.com, robert.moore@intel.com,
sunilvl@ventanamicro.com, apatel@ventanamicro.com,
Himanshu Chauhan <hchauhan@ventanamicro.com>
Subject: [RFC PATCH v2 08/10] riscv: Introduce HEST SSE notification handlers
Date: Wed, 29 Oct 2025 16:56:46 +0530 [thread overview]
Message-ID: <20251029112649.3811657-9-hchauhan@ventanamicro.com> (raw)
In-Reply-To: <20251029112649.3811657-1-hchauhan@ventanamicro.com>
Add config option to enable SSE in APEI. When it is enabled, functions
to register/unregister a ghes entry with SSE are avilable along with
low and high priority event handers. If a SSE notification type is
determined, a ghes common handler to handle an error event is registered.
Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
---
drivers/acpi/apei/Kconfig | 5 ++
drivers/acpi/apei/ghes.c | 101 +++++++++++++++++++++++++++++++++-----
2 files changed, 95 insertions(+), 11 deletions(-)
diff --git a/drivers/acpi/apei/Kconfig b/drivers/acpi/apei/Kconfig
index 070c07d68dfb..ada95a50805f 100644
--- a/drivers/acpi/apei/Kconfig
+++ b/drivers/acpi/apei/Kconfig
@@ -46,6 +46,11 @@ config ACPI_APEI_SEA
depends on ARM64 && ACPI_APEI_GHES
default y
+config ACPI_APEI_SSE
+ bool
+ depends on RISCV && RISCV_SBI_SSE && ACPI_APEI_GHES
+ default y
+
config ACPI_APEI_MEMORY_FAILURE
bool "APEI memory error recovering support"
depends on ACPI_APEI && MEMORY_FAILURE
diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c
index f2cbd7414faf..3c47249245d1 100644
--- a/drivers/acpi/apei/ghes.c
+++ b/drivers/acpi/apei/ghes.c
@@ -17,6 +17,8 @@
* Author: Huang Ying <ying.huang@intel.com>
*/
+#include <linux/err.h>
+#include <linux/riscv_sbi_sse.h>
#include <linux/arm_sdei.h>
#include <linux/kernel.h>
#include <linux/moduleparam.h>
@@ -97,6 +99,11 @@
#define FIX_APEI_GHES_SDEI_CRITICAL __end_of_fixed_addresses
#endif
+#ifndef CONFIG_RISCV_SBI_SSE
+#define FIX_APEI_GHES_SSE_LOW_PRIORITY __end_of_fixed_addresses
+#define FIX_APEI_GHES_SSE_HIGH_PRIORITY __end_of_fixed_addresses
+#endif
+
static ATOMIC_NOTIFIER_HEAD(ghes_report_chain);
static inline bool is_hest_type_generic_v2(struct ghes *ghes)
@@ -1530,6 +1537,63 @@ static int apei_sdei_unregister_ghes(struct ghes *ghes)
return sdei_unregister_ghes(ghes);
}
+#if defined(CONFIG_ACPI_APEI_SSE)
+/* SSE Handlers */
+static int __ghes_sse_callback(struct ghes *ghes,
+ enum fixed_addresses fixmap_idx)
+{
+ if (!ghes_in_nmi_queue_one_entry(ghes, fixmap_idx)) {
+ irq_work_queue(&ghes_proc_irq_work);
+
+ return 0;
+ }
+
+ return -ENOENT;
+}
+
+/* Low priority */
+static int ghes_sse_lo_callback(u32 event_num, void *arg, struct pt_regs *regs)
+{
+ static DEFINE_RAW_SPINLOCK(ghes_notify_lock_sse_lo);
+ struct ghes *ghes = arg;
+ int err;
+
+ raw_spin_lock(&ghes_notify_lock_sse_lo);
+ err = __ghes_sse_callback(ghes, FIX_APEI_GHES_SSE_LOW_PRIORITY);
+ raw_spin_unlock(&ghes_notify_lock_sse_lo);
+
+ return err;
+}
+
+/* High priority */
+static int ghes_sse_hi_callback(u32 event_num, void *arg, struct pt_regs *regs)
+{
+ static DEFINE_RAW_SPINLOCK(ghes_notify_lock_sse_hi);
+ struct ghes *ghes = arg;
+ int err;
+
+ raw_spin_lock(&ghes_notify_lock_sse_hi);
+ err = __ghes_sse_callback(ghes, FIX_APEI_GHES_SSE_HIGH_PRIORITY);
+ raw_spin_unlock(&ghes_notify_lock_sse_hi);
+
+ return err;
+}
+
+static int apei_sse_register_ghes(struct ghes *ghes)
+{
+ return sse_register_ghes(ghes, ghes_sse_lo_callback,
+ ghes_sse_hi_callback);
+}
+
+static int apei_sse_unregister_ghes(struct ghes *ghes)
+{
+ return sse_unregister_ghes(ghes);
+}
+#else /* CONFIG_ACPI_APEI_SSE */
+static int apei_sse_register_ghes(struct ghes *ghes) { return -ENOTSUPP; }
+static int apei_sse_unregister_ghes(struct ghes *ghes) { return -ENOTSUPP; }
+#endif
+
static int ghes_probe(struct platform_device *ghes_dev)
{
struct acpi_hest_generic *generic;
@@ -1576,6 +1640,15 @@ static int ghes_probe(struct platform_device *ghes_dev)
pr_warn(GHES_PFX "Generic hardware error source: %d notified via local interrupt is not supported!\n",
generic->header.source_id);
goto err;
+ case ACPI_HEST_NOTIFY_SSE:
+ if (!IS_ENABLED(CONFIG_ACPI_APEI_SSE)) {
+ pr_warn(GHES_PFX "Generic hardware error source: %d "
+ "notified via SSE is not supported\n",
+ generic->header.source_id);
+ rc = -ENOTSUPP;
+ goto err;
+ }
+ break;
default:
pr_warn(FW_WARN GHES_PFX "Unknown notification type: %u for generic hardware error source: %d\n",
generic->notify.type, generic->header.source_id);
@@ -1639,6 +1712,18 @@ static int ghes_probe(struct platform_device *ghes_dev)
if (rc)
goto err;
break;
+
+ case ACPI_HEST_NOTIFY_SSE:
+ rc = apei_sse_register_ghes(ghes);
+ if (rc) {
+ pr_err(GHES_PFX "Failed to register for SSE notification"
+ " on vector %d\n",
+ generic->notify.vector);
+ goto err;
+ }
+ pr_err(GHES_PFX "Registered SSE notification on vector %d\n",
+ generic->notify.vector);
+ break;
default:
BUG();
}
@@ -1668,7 +1753,6 @@ static int ghes_probe(struct platform_device *ghes_dev)
static void ghes_remove(struct platform_device *ghes_dev)
{
- int rc;
struct ghes *ghes;
struct acpi_hest_generic *generic;
@@ -1702,16 +1786,11 @@ static void ghes_remove(struct platform_device *ghes_dev)
ghes_nmi_remove(ghes);
break;
case ACPI_HEST_NOTIFY_SOFTWARE_DELEGATED:
- rc = apei_sdei_unregister_ghes(ghes);
- if (rc) {
- /*
- * Returning early results in a resource leak, but we're
- * only here if stopping the hardware failed.
- */
- dev_err(&ghes_dev->dev, "Failed to unregister ghes (%pe)\n",
- ERR_PTR(rc));
- return;
- }
+ apei_sdei_unregister_ghes(ghes);
+ break;
+
+ case ACPI_HEST_NOTIFY_SSE:
+ apei_sse_unregister_ghes(ghes);
break;
default:
BUG();
--
2.43.0
next prev parent reply other threads:[~2025-10-29 11:27 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-29 11:26 [RFC PATCH v2 00/10] Add RAS support for RISC-V architecture Himanshu Chauhan
2025-10-29 11:26 ` [RFC PATCH v2 01/10] riscv: Define ioremap_cache for RISC-V Himanshu Chauhan
2025-10-29 11:26 ` [RFC PATCH v2 02/10] riscv: Define arch_apei_get_mem_attribute " Himanshu Chauhan
2025-10-29 11:26 ` [RFC PATCH v2 03/10] acpi: Introduce SSE in HEST notification types Himanshu Chauhan
2025-11-05 8:33 ` Clément Léger
2025-10-29 11:26 ` [RFC PATCH v2 04/10] riscv: Add fixmap indices for GHES IRQ and SSE contexts Himanshu Chauhan
2025-11-05 8:41 ` Clément Léger
2025-10-29 11:26 ` [RFC PATCH v2 05/10] riscv: conditionally compile GHES NMI spool function Himanshu Chauhan
2025-10-29 11:26 ` [RFC PATCH v2 06/10] riscv: Add functions to register ghes having SSE notification Himanshu Chauhan
2025-11-05 10:33 ` Clément Léger
2025-10-29 11:26 ` [RFC PATCH v2 07/10] riscv: Add RISC-V entries in processor type and ISA strings Himanshu Chauhan
2025-10-29 11:26 ` Himanshu Chauhan [this message]
2025-10-29 11:26 ` [RFC PATCH v2 09/10] riscv: Select HAVE_ACPI_APEI required for RAS Himanshu Chauhan
2025-10-29 11:26 ` [RFC PATCH v2 10/10] riscv: Enable APEI GHES driver in defconfig Himanshu Chauhan
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