From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CF7542853EE; Tue, 13 Jan 2026 16:32:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.17 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768321937; cv=none; b=OYFZPJrU+0yBiO6zEWwxYkH1o61hQAOQ9N3StVqoSRbyXcvdaPbP6yf1Q1xq2UvpzX5/ea8IGDEwPy12Ix/tsZB8BdpWcQXrAFGLOUs8IImLerCMmckwdfIlTJFDo7M/2VDeHKvxZJIqfuGjpzZJKpTSK5rR4X64cg+0pdbXgdQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768321937; c=relaxed/simple; bh=weLzHqCLkqA/kFc3xBkiJih9ujw+y8wFHVU9xmh7dZI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=UE7PFz5mcu3hGDa8zsenlWXM3j9qzXEG7GjOPJWR330FVx9rDP3BYCPl3k1ZJqg2vHbrN5RLnRZr2ExVZnoiAmgliTdeiQ7NyyeQ3hlPOdRYPJ/FxLhrF2lWAxGNJap4LnJyv+60Ll3D9Qb80/Wzbsxyd3claCvNqJomMaLbYTw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=L3PawKU9; arc=none smtp.client-ip=192.198.163.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="L3PawKU9" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1768321936; x=1799857936; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=weLzHqCLkqA/kFc3xBkiJih9ujw+y8wFHVU9xmh7dZI=; b=L3PawKU9mxrzFT42elz3dj6EVdMRnHacOugwCz2e8GFHAYdPINdD2Krj vW7q3AJGeuNE5aZxtDXI27qTyFF/tvhz1YPXjrGo/IC+MO1iMQz9i3K0p YcfpVEqk0+782uI6z4LHNiKgJxwqQCEXCrzVzG10hFdGFkCwpYjQlvz6r lx5IkT1GjcARqT9Hel4okIuN7L9CNybafATKMpFratf6cPOwwFcUXL3Bb 0aBLHFQUrwl9nmTDUHPy2TCiHNzH6jUOcbnb1f+p+Q0g2/bSmsYpTLH0B StVia1xrueTx+HLtrv/htmfGDittydjcd9icruyDdg+0PwXyHhPtqQoA/ Q==; X-CSE-ConnectionGUID: uud8JUFjRbe1FZXo8dxOLg== X-CSE-MsgGUID: zGa4oC8+R4KRn16zdZzu+g== X-IronPort-AV: E=McAfee;i="6800,10657,11670"; a="69521021" X-IronPort-AV: E=Sophos;i="6.21,222,1763452800"; d="scan'208";a="69521021" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jan 2026 08:32:15 -0800 X-CSE-ConnectionGUID: sxFptwIfSramcC3FbHyPdA== X-CSE-MsgGUID: X1IMI4fcSq6h3YrnvU2i8A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,222,1763452800"; d="scan'208";a="204060131" Received: from bnilawar-desk2.iind.intel.com ([10.190.239.41]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jan 2026 08:32:11 -0800 From: Badal Nilawar To: intel-xe@lists.freedesktop.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org Cc: anshuman.gupta@intel.com, rafael@kernel.org, lenb@kernel.org, bhelgaas@google.com, ilpo.jarvinen@linux.intel.com, rodrigo.vivi@intel.com, varun.gupta@intel.com, ville.syrjala@linux.intel.com, uma.shankar@intel.com, karthik.poosa@intel.com, matthew.auld@intel.com, sk.anirban@intel.com, raag.jadav@intel.com Subject: [PATCH v6 04/12] drm/xe/vrsr: Detect VRSR Capability Date: Tue, 13 Jan 2026 22:12:05 +0530 Message-ID: <20260113164200.1151788-18-badal.nilawar@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260113164200.1151788-14-badal.nilawar@intel.com> References: <20260113164200.1151788-14-badal.nilawar@intel.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Anshuman Gupta Detect VRAM Self Refresh(vrsr) Capability. Reviewed-by: Rodrigo Vivi Signed-off-by: Anshuman Gupta --- drivers/gpu/drm/xe/regs/xe_regs.h | 3 +++ drivers/gpu/drm/xe/xe_device_types.h | 4 ++++ drivers/gpu/drm/xe/xe_pm.c | 26 ++++++++++++++++++++++++++ 3 files changed, 33 insertions(+) diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe_regs.h index ad93c57edd17..153c0a3c98d2 100644 --- a/drivers/gpu/drm/xe/regs/xe_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_regs.h @@ -57,6 +57,9 @@ #define MTL_MPE_FREQUENCY XE_REG(0x13802c) #define MTL_RPE_MASK REG_GENMASK(8, 0) +#define VRAM_SR_CAPABILITY XE_REG(0x138144) +#define VRAM_SR_SUPPORTED REG_BIT(0) + #define VF_CAP_REG XE_REG(0x1901f8, XE_REG_OPTION_VF) #define VF_CAP REG_BIT(0) diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h index a7e9d981618c..17a577772794 100644 --- a/drivers/gpu/drm/xe/xe_device_types.h +++ b/drivers/gpu/drm/xe/xe_device_types.h @@ -576,6 +576,9 @@ struct xe_device { /** @d3cold.allowed: Indicates if d3cold is a valid device state */ bool allowed; + /** @d3cold.vrsr_capable: Indicates if d3cold VRAM Self Refresh is supported */ + bool vrsr_capable; + /** * @d3cold.vram_threshold: * @@ -586,6 +589,7 @@ struct xe_device { * Default threshold value is 300mb. */ u32 vram_threshold; + /** @d3cold.lock: protect vram_threshold */ struct mutex lock; } d3cold; diff --git a/drivers/gpu/drm/xe/xe_pm.c b/drivers/gpu/drm/xe/xe_pm.c index fa607be299a7..18a44b395559 100644 --- a/drivers/gpu/drm/xe/xe_pm.c +++ b/drivers/gpu/drm/xe/xe_pm.c @@ -13,15 +13,18 @@ #include #include "display/xe_display.h" +#include "regs/xe_regs.h" #include "xe_bo.h" #include "xe_bo_evict.h" #include "xe_device.h" +#include "xe_force_wake.h" #include "xe_ggtt.h" #include "xe_gt.h" #include "xe_gt_idle.h" #include "xe_i2c.h" #include "xe_irq.h" #include "xe_late_bind_fw.h" +#include "xe_mmio.h" #include "xe_pcode.h" #include "xe_pxp.h" #include "xe_sriov_vf_ccs.h" @@ -318,6 +321,28 @@ static bool xe_pm_pci_d3cold_capable(struct xe_device *xe) return true; } +static bool xe_pm_vrsr_capable(struct xe_device *xe) +{ + struct xe_mmio *mmio = xe_root_tile_mmio(xe); + unsigned int fw_ref; + struct xe_gt *gt; + u32 val; + + gt = xe_root_mmio_gt(xe); + + if (!xe->info.probe_display) + return false; + + fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL); + if (!fw_ref) + return false; + + val = xe_mmio_read32(mmio, VRAM_SR_CAPABILITY); + xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL); + + return val & VRAM_SR_SUPPORTED; +} + static void xe_pm_runtime_init(struct xe_device *xe) { struct device *dev = xe->drm.dev; @@ -462,6 +487,7 @@ int xe_pm_init(struct xe_device *xe) err = xe_pm_set_vram_threshold(xe, vram_threshold); if (err) goto err_unregister; + xe->d3cold.vrsr_capable = xe_pm_vrsr_capable(xe); } xe_pm_runtime_init(xe); -- 2.52.0