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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by SA2PEPF00003AE7.mail.protection.outlook.com (10.167.248.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9846.18 via Frontend Transport; Thu, 23 Apr 2026 19:14:52 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 23 Apr 2026 12:14:41 -0700 Received: from vidyas-server.nvidia.com (10.126.231.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 23 Apr 2026 12:14:35 -0700 From: Vidya Sagar To: , , , , , , , , , , , , CC: , , , , , , , , , Vidya Sagar Subject: [PATCH V1 0/3] ACPI/IORT: Honor Root Complex PASID descriptors on SMMUv3 Date: Fri, 24 Apr 2026 00:44:14 +0530 Message-ID: <20260423191417.2031652-1-vidyas@nvidia.com> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003AE7:EE_|DM6PR12MB4404:EE_ X-MS-Office365-Filtering-Correlation-Id: 3f33e373-f167-4368-80ed-08dea16c98f8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|36860700016|82310400026|921020|56012099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: bWQZZPcPzzXQzCa0JTWaX169jnNvEef6JUpqAfALcyzRS6lggv3K8BgFwkqNWNP/BVRXWkxsOi8vhkeuT0YoRiRza2t/H7a2mMtOUFMrSTJolgGSAb+jv9SroBRF54TTQj2EqMFhtQIky/1ZATMUOsltjc5Aguqgoe2d9Vo2ZjWOYgEU8oSweELaguX1+a41c3VgWkVnx04/IsCyIo9iN1vcdBpAKp+eojFlphqC+a+P4Sdc4vCim/FxWFsuvOpae/3f3+oYD92dMntTNm0gSDZ4v3BRlvNt1USgckmCKvPN2mzNmrW7aIXpQJ87UTdA8daPGsfOAhwXX6oAxYdFF6t78RAWkSY0Vcm0kNGiKcRtV4z8TMsHyM/asXXIQJVsnAqn9AJDjKm+VXIXrc0H8xgmUncWTWQUY6gVE79FrJR2hjS9DaOieS1fD3pV6cmF X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Apr 2026 19:14:52.7054 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3f33e373-f167-4368-80ed-08dea16c98f8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003AE7.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4404 Hi, This series enhances Linux to read and honor the Root Complex (RC) PASID descriptors introduced by IORT Issue E.c (ARM DEN 0049E.c, January 2022, RC node revision 4): - PASID Capabilities at byte offset 33, bits[4:0] = Max PASID Width. - Flags at byte offset 36, bit 0 = "Root Complex supports PASID". Both fields have been spec'd for over four years but are not consumed anywhere in the tree. Worse, include/acpi/actbl2.h only covers the PASID Capabilities field - the trailing "u8 reserved[]" flexible array stops just before the Flags field at offset 36, so even firmware that populates it cannot be read today. The existing ACPI_IORT_PRI_SUPPORTED, ACPI_IORT_PASID_FWD_SUPPORTED and ACPI_IORT_PASID_MAX_WIDTH macros are dead code, and ACPICA upstream has the same gap. Today arm_smmu_enable_pasid() calls pci_enable_pasid() for any PCI master with a PASID capability, regardless of whether the upstream RC actually supports PASID and regardless of the RC's declared Max PASID Width. On a platform whose RC cannot forward PASID to the SMMU, this enables the PCIe PASID capability unnecessarily on the endpoint (the traffic then gets dropped upstream) and sets a non-zero master->ssid_bits, which complicates teardown ordering with ATS (see the comment block in arm_smmu_probe_device() for that ordering constraint). The series fixes this in three bite-sized patches, modeled on the CANWBS support from commit 807404d66fcf ("ACPI/IORT: Support CANWBS memory access flag"): Patch 1 (ACPICA): extend struct acpi_iort_root_complex to cover the offset-36 Flags field and add the ACPI_IORT_RC_PASID_SUPPORTED mask. With #pragma pack(1) already in effect for actbl2.h, this lands the new field at the spec-mandated absolute offset 36. Patch 2 (ACPI/IORT): add three static helpers that read the new RC PASID fields (guarded by node->revision >= 4 where appropriate), set two new iommu_fwspec flags from iort_iommu_configure_id(), and expose two device-facing wrappers so IOMMU drivers can clamp endpoint PASID widths without walking the IORT themselves. Stubs for !CONFIG_ACPI_IORT live in include/linux/acpi_iort.h. IOMMU_FWSPEC_PCI_RC_PASID (bit 2): RC declares PASID support IOMMU_FWSPEC_PCI_RC_PASID_FWD (bit 3): RC forwards PASID on translated transactions Patch 3 (arm-smmu-v3): consume the new fwspec flag and the new max-width helper in arm_smmu_enable_pasid(). If the RC explicitly declares no PASID support, skip pci_enable_pasid() silently. Otherwise clamp num_pasids by min(endpoint cap, 1 << RC width) and only proceed when the effective count is > 1. Policy: all new gating is conditional on iort_pci_rc_pasid_max_width_known(), i.e. the presence of an IORT RC node at revision >= 4. Platforms booting with older IORT firmware (RC node revision 0..3) see no behavioural change and continue to enable PASID purely on the basis of the endpoint capability. This keeps the series safe for platforms that ship pre-E.c tables. Out of scope intentionally: - Wiring the new fwspec flags into Intel/AMD IOMMU drivers - IORT is ARM-only. - Consuming IOMMU_FWSPEC_PCI_RC_PASID_FWD in arm-smmu-v3 beyond the existing CD/STE programming. The fwspec flag is plumbed now so future work (e.g. gating PASID forwarding hints in STE.S1DSS) has the information available. - Exposing a "pasid-num-bits" software node property for PCI devices, parallel to what iort_named_component_init() already does for named components. The direct helper is simpler and avoids creating a software node per RC. Thanks, Vidya Sagar Vidya Sagar (3): ACPICA: IORT: Add Root Complex PASID Flags field ACPI/IORT: Plumb Root Complex PASID descriptors into iommu_fwspec iommu/arm-smmu-v3: Honor IORT Root Complex PASID descriptors drivers/acpi/arm64/iort.c | 80 +++++++++++++++++++++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 26 ++++++- include/acpi/actbl2.h | 6 +- include/linux/acpi_iort.h | 6 ++ include/linux/iommu.h | 4 ++ 5 files changed, 118 insertions(+), 4 deletions(-) -- 2.25.1