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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by BN1PEPF0000467F.mail.protection.outlook.com (10.167.243.84) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9846.18 via Frontend Transport; Thu, 23 Apr 2026 19:15:25 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 23 Apr 2026 12:15:08 -0700 Received: from vidyas-server.nvidia.com (10.126.231.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 23 Apr 2026 12:15:02 -0700 From: Vidya Sagar To: , , , , , , , , , , , , CC: , , , , , , , , , Vidya Sagar Subject: [PATCH V1 3/3] iommu/arm-smmu-v3: Honor IORT Root Complex PASID descriptors Date: Fri, 24 Apr 2026 00:44:17 +0530 Message-ID: <20260423191417.2031652-4-vidyas@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260423191417.2031652-1-vidyas@nvidia.com> References: <20260423191417.2031652-1-vidyas@nvidia.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF0000467F:EE_|DS7PR12MB5885:EE_ X-MS-Office365-Filtering-Correlation-Id: 9915348e-ce9d-4443-7998-08dea16cac8b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|7416014|376014|36860700016|1800799024|22082099003|56012099003|18002099003|921020; X-Microsoft-Antispam-Message-Info: /jsowtGX5uj51O5JDRjJ487V1QdqpexwqLkYOH5szqHQmlB5RiJ2BkSFaf4DvuoUi23CT+7b4PqOFIgEBujOA/dMSWnrd1LFysQGZV1fCnSjx8Cz63GF7plwH/0+D6eIdOHAFkGai5sMJk6DEbePqwMPSniYx5Xo+NM0oMSxGV4UkH/rmdkuyeqkPwf2wu3wiDqHcNn7010y+ZeLOObNT/D71EyBDw4g+4qdz/KlGVzSyZeIjWhTLEzCNN3Tg1Rf6RPGBUJlLJYzRFndQZ2/UFgX/ORWpPHYLF4gh+Yl4JySUOWtD2FDL4WQoSDt/3qOhtVDCZZu+Vn0osO5A3vQszP/HihJ3Q3EaNm0YWo11tBkbkfNyegC4ekiCTHveLo5pECJBsNRzVyrpEEInM9iSOPXAJk2o0lDVuKGVA4P/CnUtQf0HDom5ygnjaEEijsJliodu8vQSNwp2GsVdIj1kIDtIOVFkvxiIlINCED3KDPkLqFu63fpGys3THzYwF7hdfN62gwL3o/jz72SpFQidxi7V6W4DXnbX8GBQJ13slqwIVXVxWTU0CbXpglr52PRiduiwdOAH4jF+rdz2nTYshDzXG3ILIye50FKmuWnzrTaLhFiYQ3GyLz3tbyBojW5aC36zOicZizC0rYZcyx4BnxYct5KbRZY7HpuIg5zStBQZq1vxaRBi/Ne4kRU0qt42BO5i3jSUDsxkAhL3Q0g2fOhMAJckjdmmK35JPli9efmUJuOHlFnsfwWvGHqAsRDSVHjYhGCiW8NueLihZP3ZmqIEzsSaitvpO3w8hudVB0zZ/C7PH+X+C5SCmMnCaiY X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(7416014)(376014)(36860700016)(1800799024)(22082099003)(56012099003)(18002099003)(921020);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: LAcz/Ftat0hx+VDuvsdZcpa3LoMmoYddBfsj1r4tvB0pr8zYl6XG4cZ9fVJ/U4d9laP/sfMTWMj5jKpCryqjkqxHR8Aoy5xVp3j3wJvxL/loSX+OgiZSVvJ9WYyQvVrTB1IecXA4wJHV8WfIKQVu+2ZK79Cldj0MYSgcuUepbwQPRusbYsZDgZLBbQNsT09Om33IW8zqdnHmQCr4fH82Enks1icKfpgrqRQf5yT2DMBn7p0oC9oEdWnulYW71fPOf17a3qEGvztaHP/8ymd5chP4U5ADs+8m+9ZV/W058B9rAl0XzGG2nkFnf0sApqcjbclt0jtOXhcwFJ5Al2QUHqBafp/d+vzePq4ecV3T5yNMhfVuRoyZTwadTZ2809UFzReaTUNARjYpPYplPcjgVjadq2doihxd3NGLy8B6YPqHOgHWvBwvkRYua+jUtCWP X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Apr 2026 19:15:25.4748 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9915348e-ce9d-4443-7998-08dea16cac8b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF0000467F.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5885 The SMMUv3 driver currently calls pci_enable_pasid() for any PCI master that exposes a PASID capability, regardless of whether the upstream Root Complex actually supports PASID and regardless of the RC's declared Max PASID Width. With IORT spec E.c (RC node revision >= 4) firmware reports both, so we can do better: - If the IORT Root Complex node says PASID is not supported (Flags bit 0 == 0 at byte offset 36), enabling PASID on the endpoint is futile - the RC will not forward the PASID prefix to the SMMU - so skip pci_enable_pasid() silently. - If the IORT Root Complex node reports a Max PASID Width (bits[4:0] of PASID Capabilities at offset 33), clamp the endpoint's pci_max_pasids() result by 1 << width before computing the SMMU SSID width. This prevents master->ssid_bits from exceeding what the RC can actually carry. Both behaviours are gated on iort_pci_rc_pasid_max_width_known(), i.e. RC node revision >= 4, so platforms with older IORT firmware see no behavioural change and continue to enable PASID purely on the basis of the endpoint capability. Use the new IOMMU_FWSPEC_PCI_RC_PASID fwspec flag (set by IORT) for the support check, and call iort_pci_rc_pasid_max_width_for_dev() for the width clamp; both pieces are wired up in iort_iommu_configure_id() by the previous patch. Signed-off-by: Vidya Sagar --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 26 ++++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index e8d7dbe495f0..2b269307fd33 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3071,16 +3071,28 @@ static void arm_smmu_enable_ats(struct arm_smmu_master *master) static int arm_smmu_enable_pasid(struct arm_smmu_master *master) { - int ret; - int features; - int num_pasids; + struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(master->dev); struct pci_dev *pdev; + int features, num_pasids, ret, rc_width; if (!dev_is_pci(master->dev)) return -ENODEV; pdev = to_pci_dev(master->dev); + /* + * IORT E.c (RC node revision >= 4) reports whether the root + * complex actually supports PASID. If it does not, enabling + * PASID on the endpoint is futile - the RC will not forward + * the PASID prefix - so skip silently. Older firmware is + * treated as "unknown / assume supported" to preserve the + * pre-E.c behaviour. + */ + if (fwspec && + !(fwspec->flags & IOMMU_FWSPEC_PCI_RC_PASID) && + iort_pci_rc_pasid_max_width_known(master->dev)) + return 0; + features = pci_pasid_features(pdev); if (features < 0) return features; @@ -3089,6 +3101,14 @@ static int arm_smmu_enable_pasid(struct arm_smmu_master *master) if (num_pasids <= 0) return num_pasids; + /* Clamp by what the root complex can carry, when known. */ + rc_width = iort_pci_rc_pasid_max_width_for_dev(master->dev); + if (rc_width >= 0) + num_pasids = min_t(int, num_pasids, 1 << rc_width); + + if (num_pasids <= 1) + return 0; + ret = pci_enable_pasid(pdev, features); if (ret) { dev_err(&pdev->dev, "Failed to enable PASID\n"); -- 2.25.1