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[47.54.130.67]) by smtp.gmail.com with ESMTPSA id af79cd13be357-8eb9becc72dsm1271207885a.34.2026.04.23.15.45.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Apr 2026 15:45:09 -0700 (PDT) Received: from jgg by wakko with local (Exim 4.97) (envelope-from ) id 1wG2nE-0000000GLqe-155A; Thu, 23 Apr 2026 19:45:08 -0300 Date: Thu, 23 Apr 2026 19:45:08 -0300 From: Jason Gunthorpe To: Vidya Sagar Cc: rafael@kernel.org, lenb@kernel.org, saket.dumbre@intel.com, lpieralisi@kernel.org, guohanjun@huawei.com, sudeep.holla@kernel.org, will@kernel.org, catalin.marinas@arm.com, joro@8bytes.org, robin.murphy@arm.com, nicolinc@nvidia.com, praan@google.com, vsethi@nvidia.com, sdonthineni@nvidia.com, kthota@nvidia.com, sagar.tv@gmail.com, linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, acpica-devel@lists.linux.dev, iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH V1 3/3] iommu/arm-smmu-v3: Honor IORT Root Complex PASID descriptors Message-ID: <20260423224508.GU3611611@ziepe.ca> References: <20260423191417.2031652-1-vidyas@nvidia.com> <20260423191417.2031652-4-vidyas@nvidia.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260423191417.2031652-4-vidyas@nvidia.com> On Fri, Apr 24, 2026 at 12:44:17AM +0530, Vidya Sagar wrote: > The SMMUv3 driver currently calls pci_enable_pasid() for any PCI > master that exposes a PASID capability, regardless of whether the > upstream Root Complex actually supports PASID and regardless of the > RC's declared Max PASID Width. With IORT spec E.c (RC node revision > >= 4) firmware reports both, so we can do better: > > - If the IORT Root Complex node says PASID is not supported > (Flags bit 0 == 0 at byte offset 36), enabling PASID on the > endpoint is futile - the RC will not forward the PASID prefix to > the SMMU - so skip pci_enable_pasid() silently. > > - If the IORT Root Complex node reports a Max PASID Width (bits[4:0] > of PASID Capabilities at offset 33), clamp the endpoint's > pci_max_pasids() result by 1 << width before computing the SMMU > SSID width. This prevents master->ssid_bits from exceeding what > the RC can actually carry. > > Both behaviours are gated on iort_pci_rc_pasid_max_width_known(), i.e. > RC node revision >= 4, so platforms with older IORT firmware see no > behavioural change and continue to enable PASID purely on the basis > of the endpoint capability. > > Use the new IOMMU_FWSPEC_PCI_RC_PASID fwspec flag (set by IORT) for > the support check, and call iort_pci_rc_pasid_max_width_for_dev() for > the width clamp; both pieces are wired up in > iort_iommu_configure_id() by the previous patch. > > Signed-off-by: Vidya Sagar > --- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 26 ++++++++++++++++++--- > 1 file changed, 23 insertions(+), 3 deletions(-) > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > index e8d7dbe495f0..2b269307fd33 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > @@ -3071,16 +3071,28 @@ static void arm_smmu_enable_ats(struct arm_smmu_master *master) > > static int arm_smmu_enable_pasid(struct arm_smmu_master *master) > { > - int ret; > - int features; > - int num_pasids; > + struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(master->dev); > struct pci_dev *pdev; > + int features, num_pasids, ret, rc_width; Don't reformat the code like this. Otherwise the series broadly makes sense to me Jason