From: Mauro Carvalho Chehab <mchehab@kernel.org>
To: uswg@uefi.org
Cc: taoxiaofei@huawei.com,
Mauro Carvalho Chehab <m.chehab@huawei.com>,
linux-acpi@vger.kernel.org, Jonathan Cameron <jic23@kernel.org>,
qemu-arm@nongnu.org
Subject: troubles with ARM processor type changes on UEFI 2.11
Date: Mon, 11 May 2026 15:44:37 +0200 [thread overview]
Message-ID: <20260511154437.4de20cea@foz.lan> (raw)
Hi,
I maintain ACPI HEST support on QEMU and I'm one of the Linux kernel reviewers
for the RAS subsystem. I'm also the author and maintainer of Linux rasdaemon,
responsible to handle RAS reports (including from GHES) on Linux.
There is an incompatible change at UEFI 2.11 spec at Section N.2.4.4.1,
which, according with UEFI 2.11 changelog, it is related to this issue:
2462 - Fix the Type mnemonic description in the ARM Processor Error Information Structure
This is the second time the specs changed the meaning of the type field
inside the ARM processor error info:
- Before UEFI 2.9A, the spec has a list of values for error type.
From the specs, type, at offset 4 was described as:
- Cache error
- TLB Error
- Bus Error
- Micro-architectural Error
All other values are reserved
Yet, there was no information about how this would be encoded.
- UEFI 2.9A defined the actual expected values as:
- Bit 1 - Cache Error
- Bit 2 - TLB Error
- Bit 3 - Bus Error
- Bit 4 - Micro-architectural Error
All other values are reserved
However, even being an incompatible change, the spec didn't change
version field at Section N.2.4.4.1.
Linux, QEMU, rasdaemon and likely several BIOS implementations
were updated accordingly.
- UEFI 2.11 changed the definition to:
- Bit 0 - Cache Error
- Bit 1 - TLB Error
- Bit 2 - Bus Error
- Bit 3 - Micro-architectural Error
All other values are reserved
Again, another incompatible change and without changing the version
field at Section N.2.4.4.1.
With the current mess, it is impossible for the OSPM (and RAS apps) to
properly map ARM processor error types, as for instance, type=2 can
mean:
- Bus error (up to UEFI 2.9)
- Cache error (UEFI 2.9A and UEFI 2.10)
- TLB error (UEFI 2.11)
Please issue an errata incrementing version number, to allow OSPM
QEMU and rasdaemon to properly interpret this field.
Thanks,
Mauro
reply other threads:[~2026-05-11 13:44 UTC|newest]
Thread overview: [no followups] expand[flat|nested] mbox.gz Atom feed
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260511154437.4de20cea@foz.lan \
--to=mchehab@kernel.org \
--cc=jic23@kernel.org \
--cc=linux-acpi@vger.kernel.org \
--cc=m.chehab@huawei.com \
--cc=qemu-arm@nongnu.org \
--cc=taoxiaofei@huawei.com \
--cc=uswg@uefi.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox