From: Dave Jiang <dave.jiang@intel.com>
To: linux-acpi@vger.kernel.org, linux-cxl@vger.kernel.org
Cc: rafael@kernel.org, tony.luck@intel.com, bp@alien8.de,
guohanjun@huawei.com, mchehab@kernel.org,
xueshuai@linux.alibaba.com, terry.bowman@amd.com,
Ben Cheatham <benjamin.cheatham@amd.com>
Subject: [PATCH v2 0/7] ACPI: APEI: GHES: Collection of fixes for issues reported by sashiko
Date: Tue, 14 Jul 2026 16:18:28 -0700 [thread overview]
Message-ID: <20260714231835.303081-1-dave.jiang@intel.com> (raw)
A collection of fixes for pre-existing issues reported by sashiko-bot while
reviewing patches.
1/7: Bound the CXL event record copy to the firmware section length.
2/7: Validate the CXL protocol error section length before the RAS cap copy.
3/7: Avoid populating software AER metadata from the raw hardware buffer.
4/7: Validate the PCIe error section length before payload access.
5/7: Fix the CONFIG_ACPI_APEI_PCIEAER guard typo in extlog.c.
6/7: Defer CXL protocol error handling to avoid a lock inversion.
7/7: Validate the memory error section length before payload access.
v1: https://lore.kernel.org/linux-cxl/20260709162807.1957783-1-dave.jiang@intel.com/
Changes since v1:
- Dropped v1 1/4 "ACPI: APEI: GHES: Use spin_lock_irqsave() for CXL CPER
work locks". Terry Bowman has a more comprehensive version of this that
he will post.
- Reordered the series so the two patches that harden extlog_print_pcie()
land before the CONFIG_ACPI_APEI_PCIEAER typo fix that activates that
code path, avoiding a bisection window where the path is live but
unhardened.
- Grew the series from 4 to 7 patches, adding four fixes for the
additional pre-existing issues Sashiko flagged on the v1 posting.
Dave Jiang (7):
ACPI: APEI: GHES: Bound CXL event record copy to the firmware section
length
ACPI: APEI: GHES: Validate CXL protocol error section length before
RAS cap copy
ACPI: extlog: Avoid populating software AER metadata from raw hardware
buffer
ACPI: extlog: Validate PCIe error section length before payload access
ACPI: extlog: Fix CONFIG_ACPI_APEI_PCIEAER guard typo
ACPI: extlog: Defer CXL protocol error handling to avoid lock
inversion
ACPI: APEI: GHES: Validate memory error section length before payload
access
drivers/acpi/acpi_extlog.c | 40 ++++++++++++++------------------
drivers/acpi/apei/ghes.c | 35 +++++++++++++++++++++-------
drivers/acpi/apei/ghes_helpers.c | 22 +++++++++++++++++-
include/acpi/ghes.h | 4 ++++
include/cxl/event.h | 4 ++--
5 files changed, 71 insertions(+), 34 deletions(-)
base-commit: a13c140cc289c0b7b3770bce5b3ad42ab35074aa
--
2.55.0
next reply other threads:[~2026-07-14 23:18 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-14 23:18 Dave Jiang [this message]
2026-07-14 23:18 ` [PATCH v2 1/7] ACPI: APEI: GHES: Bound CXL event record copy to the firmware section length Dave Jiang
2026-07-14 23:18 ` [PATCH v2 2/7] ACPI: APEI: GHES: Validate CXL protocol error section length before RAS cap copy Dave Jiang
2026-07-14 23:18 ` [PATCH v2 3/7] ACPI: extlog: Avoid populating software AER metadata from raw hardware buffer Dave Jiang
2026-07-14 23:18 ` [PATCH v2 4/7] ACPI: extlog: Validate PCIe error section length before payload access Dave Jiang
2026-07-14 23:18 ` [PATCH v2 5/7] ACPI: extlog: Fix CONFIG_ACPI_APEI_PCIEAER guard typo Dave Jiang
2026-07-14 23:18 ` [PATCH v2 6/7] ACPI: extlog: Defer CXL protocol error handling to avoid lock inversion Dave Jiang
2026-07-14 23:18 ` [PATCH v2 7/7] ACPI: APEI: GHES: Validate memory error section length before payload access Dave Jiang
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