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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by DM2PEPF00003FC8.mail.protection.outlook.com (10.167.23.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.292.8 via Frontend Transport; Mon, 3 Aug 2026 22:18:27 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.41; Mon, 3 Aug 2026 17:18:26 -0500 From: Terry Bowman To: Jonathan Cameron , Dave Jiang , Alison Schofield , Vishal Verma , Davidlohr Bueso , "Bjorn Helgaas" , "Rafael J . Wysocki" , Jonathan Corbet , CC: Tony Luck , Borislav Petkov , "Hanjun Guo" , Mauro Carvalho Chehab , "Shuai Xue" , Len Brown , Ira Weiny , Li Ming , Shuah Khan , Ben Cheatham , Richard Cheng , Robert Richter , , , , Subject: [PATCH v19 01/14] cxl/ras: Fix cxl_rch_get_aer_info() out-of-bounds AER register read Date: Mon, 3 Aug 2026 17:17:57 -0500 Message-ID: <20260803221810.3685703-2-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260803221810.3685703-1-terry.bowman@amd.com> References: <20260803221810.3685703-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM2PEPF00003FC8:EE_|CYXPR12MB9338:EE_ X-MS-Office365-Filtering-Correlation-Id: 74843111-3eff-466a-83ac-08def1ad24b4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|23010399003|7416014|36860700016|1800799024|82310400026|10067099003|56012099006|11063799006|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: nP/dPD0f0Mt+hyJLkp6uNmLX/qDbS8D8Vgo+iD94oAqTRBmTAQkFIQY7LE3fT24CFBoZA0Bg4Azb1TmTaZVO5P82s52rNMvH8a6EK3Nq/gNriyb9XmP/Q1OW2epPXYwAEgMWfe8l3ScBD/uzY33V/szRI7MRTAahLryKXWw1rsq70uBz6fB4LErmPxgrPLGr4xcoTJSUKgRZJA96YfxjwACFRoYOX1P5U6/6WInnVqLAYCSQsf+ty3dZ0UQ9ReG2n0NZC8lLaSn949WhOCp8f5sLhTw4+G+zvbU8YxQFdze64u7poieOhGJ1xGzJyrj7bjRnTZbPsS6w2YxtUFce2KOyOX2mqNXLPPTlsDN0DWu79S0P8Fa/MZTJiLT1zSeCG/JIcco1oMTexvyoa9rsuAPSG/Ckj4DuAuvTXbUeaNCPugdPO93aa5bR7WrJQAMHZV69SaDSH+uVjj2xN3CzRvx1l2AfteujU44U9dZ3SQBK9y6GLLug7AfB1a3bgePQEHEtZQPYUYef+DV9Fj+Qgzo8v6hxQvatOhe5aEZ1JPv3ampTHg12PbUkhC8AQTL+vKbRxjJ7OWtosy0vnfGVl8hWwAAg5KtZ51CErkmzkH0rx00guUVcC3L59hnVgK0EMzSTDazlckCP9fP46X/ReDsVFMv82V3tWDusTeD/4LSWsxnEzjToN9/BxAxK84wRO/TILknvN/PxVp1Pd4l/VQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(23010399003)(7416014)(36860700016)(1800799024)(82310400026)(10067099003)(56012099006)(11063799006)(22082099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: pAhV3yqlodjbiLq7vHeX3a1xpw5CaSmrtXPxSZ7a7gH5CA7/EeiRROIgoGC6yXsxmYG31bBWTkUpbLJFDNyt2aZr62hBp5z39mytFMN35B7IGKOL05Lk4D5Z9AtuFoLjm6i2mAMZMUXqD09SFhFJSoq21WOniIxg8vxOmgrG5jNyimDWUBNSJaC5s3QBVESstkWU0TLehp5/uENEw5v1WE5mxxy7QtS++AQpwKDZhn7/bCcqZE3HMzlkWXvH02sDNx20U/B/opKy0y0TV9HYKIxnHRFC/ZK2zYLhi9TU6BXiwDP+JySy725N6ip3t93OC6MDqa1yik4KqgPY7mDmatCG+R6lSXBx0G1irT+8S11V6mWR677qINTJeZ5uixl5DQBx0TlcrfmHX+xWnoARojePj9Sn312zeaHWYGHg7eMvT1GpnVrqx38E3Pooeo/d X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Aug 2026 22:18:27.9846 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 74843111-3eff-466a-83ac-08def1ad24b4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM2PEPF00003FC8.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYXPR12MB9338 cxl_rch_get_aer_info() copies the RCH Downstream Port AER capability from the RCRB MMIO block using a readl() loop bounded by sizeof(struct aer_capability_regs). This struct is a software layout and its embedded struct pcie_tlp_log is larger than the on-wire AER capability. As a result the loop reads past the mapped AER register block. The over-read also populates the software-only tail fields including header_log.header_len. An out-of-range header_len passed to pcie_print_tlp_log() can then loop past the header log buffer and cause a second out-of-bounds read. The read was correct when introduced, but struct pcie_tlp_log has since grown (Header Log and TLP Prefix Log sizes, header_len and flit fields), so sizeof(struct aer_capability_regs) no longer matches the physical AER capability. Bound the read to the physical AER registers, header through the 16 byte Header Log. Zero the destination first so the software-only fields are deterministic. Fixes: 6ac07883dbb5 ("cxl/pci: Add RCH downstream port error logging") Reported-by: Sashiko Cc: stable@vger.kernel.org Signed-off-by: Terry Bowman --- Changes in v18 -> v19: - New patch, split from "cxl/ras: Fix cxl_rch_get_aer_severity() wrong severity register". Addresses out-of-bounds RCRB MMIO read that Sashiko flagged against the combined v18 patch. --- drivers/cxl/core/ras_rch.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/cxl/core/ras_rch.c b/drivers/cxl/core/ras_rch.c index 0a8b3b9b63884..8a3965edaa12c 100644 --- a/drivers/cxl/core/ras_rch.c +++ b/drivers/cxl/core/ras_rch.c @@ -58,13 +58,28 @@ void cxl_disable_rch_root_ints(struct cxl_dport *dport) static bool cxl_rch_get_aer_info(void __iomem *aer_base, struct aer_capability_regs *aer_regs) { - int read_cnt = sizeof(struct aer_capability_regs) / sizeof(u32); + /* + * Bound the copy to the physically-defined AER registers (header + * through the 16-byte Header Log). struct aer_capability_regs is a + * software layout whose embedded struct pcie_tlp_log is larger than + * the on-wire AER capability; copying sizeof(*aer_regs) would + * over-read the RCRB-mapped MMIO block. + */ + int read_cnt = (PCI_ERR_HEADER_LOG + 16) / sizeof(u32); u32 *aer_regs_buf = (u32 *)aer_regs; int n; if (!aer_base) return false; + /* + * Zero the destination so the software-only tail fields + * (e.g. header_log.header_len) are deterministic rather than + * left as uninitialized stack, which could drive a bogus loop + * length in pcie_print_tlp_log(). + */ + memset(aer_regs, 0, sizeof(*aer_regs)); + /* Use readl() to guarantee 32-bit accesses */ for (n = 0; n < read_cnt; n++) aer_regs_buf[n] = readl(aer_base + n * sizeof(u32)); -- 2.34.1