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[199.106.103.254]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-34145c166cfsm1343887eec.28.2026.09.24.15.20.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Sep 2026 15:20:24 -0700 (PDT) Date: Thu, 24 Sep 2026 15:20:17 -0700 From: Jonathan Cameron To: Andre Przywara Cc: Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Catalin Marinas , Will Deacon , "Rafael J . Wysocki" , Len Brown , James Morse , Ben Horgan , Reinette Chatre , Fenghua Yu , Jonathan Cameron , Srivathsa L Rao , Ganapatrao Kulkarni , Trilok Soni , Srinivas Ramana , Niyas Sait , Lee Trager , Ritwick Sharma , Gavin Shan , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v11 08/13] arm_mpam: propagate MSC access errors for interrupt control Message-ID: <20260924152017.00004ec8@oss.qualcomm.com> In-Reply-To: <20260924152739.2865510-9-andre.przywara@arm.com> References: <20260924152739.2865510-1-andre.przywara@arm.com> <20260924152739.2865510-9-andre.przywara@arm.com> Organization: Qualcomm X-Mailer: Claws Mail 4.4.0 (GTK 3.24.51; x86_64-w64-mingw32) Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: DQ3g72w065qMaVQusPxv9y1QNWRutqbY X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI0MDA5MSBTYWx0ZWRfXyLLPwhjISkfG IcQyHDzYUlcMb7ANi78DDknVE3sj2JfOSDI9hmLXQugXTrHj/FWMDCrJaWX0qTCIUaISwocXUeo FNVtGRsM9xJHCA+9ehjGRskHP6hk32WqeJsPNDKq+lQs5s28I19C3AQbRHbDAwZ3eiJwgYMAq4a GN/bL91IaqTjkbodGTU9fWvknkys6iNqJaSF/9uDGyfbHqnm1Jqr63ERYQhApHdWjN/rKCkD5vM aafiR70g2rySlf4HPf5N8xugrRsEAbfg8oxdVoKcG2U7V2MFIdFQqIrj2bPBdw9oQ+jF3r0mjbM 7+ZPorILBs736Nrose/GjH8wmi4HtzmFdZT6kqzIBAqVdw2TrpVH4KZ5KohuRaX4p/A5th4RZBr NHC18WTg2NLuZXBOLQ3FGIJBalperrHmInxm+4HcqAYEbKdjwRwrhHzNckdGdHkY9AiMiPrZB5K bDSkh9CUN2MJr1MotVw== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI0MDA5MSBTYWx0ZWRfXwYTIyCsUfHUP Cz4AExijfhbrciJksfEjuC7xJYaisQNQpxb1vDlH3RKRs2azMxnj12SU4+QvDvGKCXQb6QlNp4g niyJEyKvWsfhX9+4NrM9NarIqT+5V+c= X-Proofpoint-ORIG-GUID: DQ3g72w065qMaVQusPxv9y1QNWRutqbY X-Authority-Analysis: v=2.4 cv=GI+dgeNK c=1 sm=1 tr=0 ts=6ab5a22a cx=c_pps a=Uww141gWH0fZj/3QKPojxA==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=kj9zAlcOel0A:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=7CQSdrXTAAAA:8 a=EUspDBNiAAAA:8 a=BicPeEsDMmYJQF04euIA:9 a=CjuIK1q_8ugA:10 a=PxkB5W3o20Ba91AHUih5:22 a=a-qgeE7W1pNrGK8U0ZQC:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-24_05,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 lowpriorityscore=0 bulkscore=0 malwarescore=0 impostorscore=0 suspectscore=0 spamscore=0 adultscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609240091 On Thu, 24 Sep 2026 17:27:34 +0200 Andre Przywara wrote: > Allow the functions dealing with interrupt registration and enablement > to check for and return errors, and propagate MSC read and write errors > from the lower level up. > This does not cover the IRQ handler yet, as this needs some more > attention. > > Signed-off-by: Andre Przywara > Reviewed-by: Srivathsa L Rao A few trivial things below. Anyhow, I don't really care about them so Reviewed-by: Jonathan Cameron > --- > drivers/resctrl/mpam_devices.c | 31 +++++++++++++++---------------- > 1 file changed, 15 insertions(+), 16 deletions(-) > > diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c > index 558efab75f911..eb26c25b9f970 100644 > --- a/drivers/resctrl/mpam_devices.c > +++ b/drivers/resctrl/mpam_devices.c > @@ -1105,7 +1105,9 @@ static int mpam_msc_hw_probe(struct mpam_msc *msc) > } > > /* Clear any stale errors */ > - mpam_msc_clear_esr(msc); > + ret = mpam_msc_clear_esr(msc); > + if (ret) > + return ret; > > spin_lock(&partid_max_lock); > mpam_partid_max = min(mpam_partid_max, msc->partid_max); > @@ -2668,9 +2670,7 @@ static int mpam_enable_msc_ecr(void *_msc) > { > struct mpam_msc *msc = _msc; > > - __mpam_write_reg(msc, MPAMF_ECR, MPAMF_ECR_INTEN); > - > - return 0; > + return __mpam_write_reg(msc, MPAMF_ECR, MPAMF_ECR_INTEN); > } > > /* This can run in mpam_disable(), and the interrupt handler on the same CPU */ > @@ -2678,9 +2678,7 @@ static int mpam_disable_msc_ecr(void *_msc) > { > struct mpam_msc *msc = _msc; > > - __mpam_write_reg(msc, MPAMF_ECR, 0); > - > - return 0; > + return __mpam_write_reg(msc, MPAMF_ECR, 0); > } > > static irqreturn_t __mpam_irq_handler(int irq, struct mpam_msc *msc) > @@ -2777,11 +2775,13 @@ static int mpam_register_irqs(void) > return err; > } > > - mutex_lock(&msc->error_irq_lock); > - msc->error_irq_req = true; > - mpam_touch_msc(msc, mpam_enable_msc_ecr, msc); > - msc->error_irq_hw_enabled = true; > - mutex_unlock(&msc->error_irq_lock); > + scoped_guard(mutex, &msc->error_irq_lock) { > + msc->error_irq_req = true; > + err = mpam_touch_msc(msc, mpam_enable_msc_ecr, msc); > + if (err) > + return err; > + msc->error_irq_hw_enabled = true; > + } Scope ends here so unless something else gets added in later patches, you could just use a guard() and reduce the noise. > } > > return 0; > @@ -2800,10 +2800,10 @@ static void mpam_unregister_irqs(void) > if (irq <= 0) > continue; > > - mutex_lock(&msc->error_irq_lock); Given you don't return early as a result this is an unrelated change. I don't really mind but in ideal world would be a separate patch. > + guard(mutex)(&msc->error_irq_lock); > if (msc->error_irq_hw_enabled) { > - mpam_touch_msc(msc, mpam_disable_msc_ecr, msc); > - msc->error_irq_hw_enabled = false; > + if (!mpam_touch_msc(msc, mpam_disable_msc_ecr, msc)) > + msc->error_irq_hw_enabled = false; > } > > if (msc->error_irq_req) { > @@ -2815,7 +2815,6 @@ static void mpam_unregister_irqs(void) > } > msc->error_irq_req = false; > } > - mutex_unlock(&msc->error_irq_lock); > } > } >