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Wysocki" , Tony Luck , Borislav Petkov , Hanjun Guo , Mauro Carvalho Chehab , Shuai Xue , Len Brown , Ben Cheatham Cc: Alison Schofield , linux-acpi@vger.kernel.org, linux-cxl@vger.kernel.org, Pei Gao Subject: [PATCH] EINJ, CXL: Use PCI domain for CXL root port error injection Date: Thu, 5 Nov 2026 10:46:41 -0800 Message-ID: <20261105184643.907678-1-alison.schofield@intel.com> X-Mailer: git-send-email 2.47.0 X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit CXL protocol error injection identifies the target root port to firmware using its PCI segment, bus, device, and function (SBDF). The segment is taken from the PCI host bridge's domain_nr, which is only populated for emulated PCI domains. On ACPI systems, firmware receives segment 0 even when the target root port belongs to a nonzero segment, identifying the wrong PCI device for error injection. Use the PCI domain of the target root port to obtain the correct segment. With the host bridge lookup removed, cxl_dport_get_sbdf() can return the SBDF directly. Reported-by: Pei Gao Fixes: 12fb28ea6b1c ("EINJ: Add CXL error type support") Signed-off-by: Alison Schofield --- The ACPI EINJ SBDF field limits the PCI segment to 8 bits, while PCI segment numbers can be 16 bits. A segment greater than 0xff would be silently truncated, potentially targeting the wrong device. I'm unsure how likely systems are to use segments above 0xff. Is this a practical concern? Would a range check to enforce the ACPI limit be warranted in a follow-up patch? --- drivers/acpi/apei/einj-cxl.c | 29 +++++++---------------------- 1 file changed, 7 insertions(+), 22 deletions(-) diff --git a/drivers/acpi/apei/einj-cxl.c b/drivers/acpi/apei/einj-cxl.c index e70a416ec925..4c8f014378bc 100644 --- a/drivers/acpi/apei/einj-cxl.c +++ b/drivers/acpi/apei/einj-cxl.c @@ -47,25 +47,12 @@ int einj_cxl_available_error_type_show(struct seq_file *m, void *v) } EXPORT_SYMBOL_NS_GPL(einj_cxl_available_error_type_show, "CXL"); -static int cxl_dport_get_sbdf(struct pci_dev *dport_dev, u64 *sbdf) +static u64 cxl_dport_get_sbdf(struct pci_dev *dport_dev) { - struct pci_bus *pbus; - struct pci_host_bridge *bridge; - u64 seg = 0, bus; + u64 seg = pci_domain_nr(dport_dev->bus); + u64 bus = dport_dev->bus->number; - pbus = dport_dev->bus; - bridge = pci_find_host_bridge(pbus); - - if (!bridge) - return -ENODEV; - - if (bridge->domain_nr != PCI_DOMAIN_NR_NOT_SET) - seg = bridge->domain_nr; - - bus = pbus->number; - *sbdf = (seg << 24) | (bus << 16) | (dport_dev->devfn << 8); - - return 0; + return (seg << 24) | (bus << 16) | (dport_dev->devfn << 8); } int einj_cxl_inject_rch_error(u64 rcrb, u64 type) @@ -87,7 +74,7 @@ EXPORT_SYMBOL_NS_GPL(einj_cxl_inject_rch_error, "CXL"); int einj_cxl_inject_error(struct pci_dev *dport, u64 type) { - u64 param4 = 0; + u64 sbdf; int rc; /* Only CXL error types can be specified */ @@ -98,11 +85,9 @@ int einj_cxl_inject_error(struct pci_dev *dport, u64 type) if (rc) return rc; - rc = cxl_dport_get_sbdf(dport, ¶m4); - if (rc) - return rc; + sbdf = cxl_dport_get_sbdf(dport); - return einj_error_inject(type, 0x4, 0, 0, 0, param4); + return einj_error_inject(type, 0x4, 0, 0, 0, sbdf); } EXPORT_SYMBOL_NS_GPL(einj_cxl_inject_error, "CXL"); base-commit: 6628e7d4c6b25c8d18f1345e3a20d21829aae7e4 -- 2.37.3