From mboxrd@z Thu Jan 1 00:00:00 1970 From: Shawn Starr Subject: Re: [3.9-rc1] irq 16: nobody cared (was [3.9-rc1] very poor interrupt responses) Date: Sun, 17 Mar 2013 22:41:28 -0400 Message-ID: <2654053.iVVmfUEvRC@segfault.sh0n.net> References: Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0968175004==" Return-path: In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: dri-devel-bounces+sf-dri-devel=m.gmane.org@lists.freedesktop.org Errors-To: dri-devel-bounces+sf-dri-devel=m.gmane.org@lists.freedesktop.org To: Yinghai Lu Cc: Harald Arnesen , Peter Hurley , Jiri Kosina , Daniel Vetter , USB list , Kernel development list , "Rafael J. Wysocki" , linux-acpi@vger.kernel.org, Alan Stern , dri-devel@lists.freedesktop.org, linux-pci@vger.kernel.org, Bjorn Helgaas , Thomas Meyer List-Id: linux-acpi@vger.kernel.org This is a multi-part message in MIME format. --===============0968175004== Content-Type: multipart/alternative; boundary="nextPart7883118.HHc0sZQR6G" Content-Transfer-Encoding: 7Bit This is a multi-part message in MIME format. --nextPart7883118.HHc0sZQR6G Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" On Friday, March 15, 2013 12:14:28 PM Yinghai Lu wrote: > On Fri, Mar 15, 2013 at 8:14 AM, Jiri Kosina wrote: > > Just a datapoint -- I have put a trivial debugging patch in place, and it > > reveals that "nobody cared" for irq 16 happens long after last > > > > I915_WRITE(GMBUS4 + reg_offset, 0); > > > > has been performed in gmbus_wait_hw_status(). On the other hand, if I > > comment out both GMBUS4 register offset writes in gmbus_wait_hw_status(), > > then it of course falls back to GPIO bit-banging, but the "nobody cared" > > for irq 16 is gone. > > > > So it seems like something gets severely confused by the I915_WRITE to > > GMBUS4 + reg_offset. So far this seems to have been reported solely on > > Lenovos as far as I can see (although a completely different types), so it > > might be some platform-specific quirk? > > > > Honestly, I still don't understand how all the GMBUS stuff relates to IRQ > > 16 at all. > > that device is using > i915 0000:00:02.0: irq 44 for MSI/MSI-X > > so can you try to boot with pci=nomsi? I can try disabling MSI with 3.9.0-0.rc2.git0.4.fc20. -rc3 is not yet available in rawhide. thanks, Shawn --nextPart7883118.HHc0sZQR6G Content-Transfer-Encoding: 7Bit Content-Type: text/html; charset="us-ascii"

On Friday, March 15, 2013 12:14:28 PM Yinghai Lu wrote:

> On Fri, Mar 15, 2013 at 8:14 AM, Jiri Kosina <jkosina@suse.cz> wrote:

> > Just a datapoint -- I have put a trivial debugging patch in place, and it

> > reveals that "nobody cared" for irq 16 happens long after last

> >

> > I915_WRITE(GMBUS4 + reg_offset, 0);

> >

> > has been performed in gmbus_wait_hw_status(). On the other hand, if I

> > comment out both GMBUS4 register offset writes in gmbus_wait_hw_status(),

> > then it of course falls back to GPIO bit-banging, but the "nobody cared"

> > for irq 16 is gone.

> >

> > So it seems like something gets severely confused by the I915_WRITE to

> > GMBUS4 + reg_offset. So far this seems to have been reported solely on

> > Lenovos as far as I can see (although a completely different types), so it

> > might be some platform-specific quirk?

> >

> > Honestly, I still don't understand how all the GMBUS stuff relates to IRQ

> > 16 at all.

>

> that device is using

> i915 0000:00:02.0: irq 44 for MSI/MSI-X

>

> so can you try to boot with pci=nomsi?

 

I can try disabling MSI with 3.9.0-0.rc2.git0.4.fc20. -rc3 is not yet available in rawhide.

 

thanks,

Shawn

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