From: Dave Jiang <dave.jiang@intel.com>
To: Ira Weiny <ira.weiny@intel.com>, Dan Williams <dan.j.williams@intel.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>,
Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Davidlohr Bueso <dave@stgolabs.net>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Ben Widawsky <bwidawsk@kernel.org>,
Steven Rostedt <rostedt@goodmis.org>,
linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
linux-acpi@vger.kernel.org, linux-cxl@vger.kernel.org
Subject: Re: [PATCH v7 7/8] cxl/test: Add specific events
Date: Tue, 9 May 2023 15:08:24 -0700 [thread overview]
Message-ID: <3d320d04-a0e6-12dd-490a-f0111c2ad98a@intel.com> (raw)
In-Reply-To: <20221216-cxl-ev-log-v7-7-2316a5c8f7d8@intel.com>
On 1/17/23 10:53 PM, Ira Weiny wrote:
> Each type of event has different trace point outputs.
>
> Add mock General Media Event, DRAM event, and Memory Module Event
> records to the mock list of events returned.
>
> Reviewed-by: Dan Williams <dan.j.williams@intel.com>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Signed-off-by: Ira Weiny <ira.weiny@intel.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
>
> ---
> Changes in v7:
> <no change>
> ---
> tools/testing/cxl/test/mem.c | 73 ++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 73 insertions(+)
>
> diff --git a/tools/testing/cxl/test/mem.c b/tools/testing/cxl/test/mem.c
> index 90a463f83ae4..00bf19a68604 100644
> --- a/tools/testing/cxl/test/mem.c
> +++ b/tools/testing/cxl/test/mem.c
> @@ -277,12 +277,85 @@ struct cxl_event_record_raw hardware_replace = {
> .data = { 0xDE, 0xAD, 0xBE, 0xEF },
> };
>
> +struct cxl_event_gen_media gen_media = {
> + .hdr = {
> + .id = UUID_INIT(0xfbcd0a77, 0xc260, 0x417f,
> + 0x85, 0xa9, 0x08, 0x8b, 0x16, 0x21, 0xeb, 0xa6),
> + .length = sizeof(struct cxl_event_gen_media),
> + .flags[0] = CXL_EVENT_RECORD_FLAG_PERMANENT,
> + /* .handle = Set dynamically */
> + .related_handle = cpu_to_le16(0),
> + },
> + .phys_addr = cpu_to_le64(0x2000),
> + .descriptor = CXL_GMER_EVT_DESC_UNCORECTABLE_EVENT,
> + .type = CXL_GMER_MEM_EVT_TYPE_DATA_PATH_ERROR,
> + .transaction_type = CXL_GMER_TRANS_HOST_WRITE,
> + /* .validity_flags = <set below> */
> + .channel = 1,
> + .rank = 30
> +};
> +
> +struct cxl_event_dram dram = {
> + .hdr = {
> + .id = UUID_INIT(0x601dcbb3, 0x9c06, 0x4eab,
> + 0xb8, 0xaf, 0x4e, 0x9b, 0xfb, 0x5c, 0x96, 0x24),
> + .length = sizeof(struct cxl_event_dram),
> + .flags[0] = CXL_EVENT_RECORD_FLAG_PERF_DEGRADED,
> + /* .handle = Set dynamically */
> + .related_handle = cpu_to_le16(0),
> + },
> + .phys_addr = cpu_to_le64(0x8000),
> + .descriptor = CXL_GMER_EVT_DESC_THRESHOLD_EVENT,
> + .type = CXL_GMER_MEM_EVT_TYPE_INV_ADDR,
> + .transaction_type = CXL_GMER_TRANS_INTERNAL_MEDIA_SCRUB,
> + /* .validity_flags = <set below> */
> + .channel = 1,
> + .bank_group = 5,
> + .bank = 2,
> + .column = {0xDE, 0xAD},
> +};
> +
> +struct cxl_event_mem_module mem_module = {
> + .hdr = {
> + .id = UUID_INIT(0xfe927475, 0xdd59, 0x4339,
> + 0xa5, 0x86, 0x79, 0xba, 0xb1, 0x13, 0xb7, 0x74),
> + .length = sizeof(struct cxl_event_mem_module),
> + /* .handle = Set dynamically */
> + .related_handle = cpu_to_le16(0),
> + },
> + .event_type = CXL_MMER_TEMP_CHANGE,
> + .info = {
> + .health_status = CXL_DHI_HS_PERFORMANCE_DEGRADED,
> + .media_status = CXL_DHI_MS_ALL_DATA_LOST,
> + .add_status = (CXL_DHI_AS_CRITICAL << 2) |
> + (CXL_DHI_AS_WARNING << 4) |
> + (CXL_DHI_AS_WARNING << 5),
> + .device_temp = { 0xDE, 0xAD},
> + .dirty_shutdown_cnt = { 0xde, 0xad, 0xbe, 0xef },
> + .cor_vol_err_cnt = { 0xde, 0xad, 0xbe, 0xef },
> + .cor_per_err_cnt = { 0xde, 0xad, 0xbe, 0xef },
> + }
> +};
> +
> static void cxl_mock_add_event_logs(struct mock_event_store *mes)
> {
> + put_unaligned_le16(CXL_GMER_VALID_CHANNEL | CXL_GMER_VALID_RANK,
> + &gen_media.validity_flags);
> +
> + put_unaligned_le16(CXL_DER_VALID_CHANNEL | CXL_DER_VALID_BANK_GROUP |
> + CXL_DER_VALID_BANK | CXL_DER_VALID_COLUMN,
> + &dram.validity_flags);
> +
> mes_add_event(mes, CXL_EVENT_TYPE_INFO, &maint_needed);
> + mes_add_event(mes, CXL_EVENT_TYPE_INFO,
> + (struct cxl_event_record_raw *)&gen_media);
> + mes_add_event(mes, CXL_EVENT_TYPE_INFO,
> + (struct cxl_event_record_raw *)&mem_module);
> mes->ev_status |= CXLDEV_EVENT_STATUS_INFO;
>
> mes_add_event(mes, CXL_EVENT_TYPE_FATAL, &hardware_replace);
> + mes_add_event(mes, CXL_EVENT_TYPE_FATAL,
> + (struct cxl_event_record_raw *)&dram);
> mes->ev_status |= CXLDEV_EVENT_STATUS_FATAL;
> }
>
>
next prev parent reply other threads:[~2023-05-09 22:08 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-18 5:53 [PATCH v7 0/8] cxl: Process event logs Ira Weiny
2023-01-18 5:53 ` [PATCH v7 1/8] cxl/mem: Read, trace, and clear events on driver load Ira Weiny
2023-01-26 21:53 ` Dan Williams
2023-01-27 0:49 ` Dan Williams
2023-01-27 19:45 ` Ira Weiny
2023-05-05 9:47 ` Huai-Cheng
2023-05-08 2:41 ` Ira Weiny
2023-05-09 21:41 ` Dave Jiang
2023-01-18 5:53 ` [PATCH v7 2/8] cxl/mem: Wire up event interrupts ira.weiny
2023-01-26 22:00 ` Dan Williams
2023-05-09 21:42 ` Dave Jiang
[not found] ` <tencent_D9D9D358330CA573E23D490C6EE13E0DC105@qq.com>
2023-05-19 1:38 ` CXL memory device not created correctly Davidlohr Bueso
2023-05-19 15:10 ` Jonathan Cameron
2023-05-19 15:20 ` Ira Weiny
2023-05-19 15:37 ` Jonathan Cameron
2023-05-31 2:18 ` Luis Chamberlain
2023-06-01 3:12 ` Ira Weiny
2023-06-01 3:46 ` Davidlohr Bueso
2023-01-18 5:53 ` [PATCH v7 3/8] cxl/mem: Trace General Media Event Record Ira Weiny
2023-05-09 21:47 ` Dave Jiang
2023-01-18 5:53 ` [PATCH v7 4/8] cxl/mem: Trace DRAM " Ira Weiny
2023-05-09 21:48 ` Dave Jiang
2023-01-18 5:53 ` [PATCH v7 5/8] cxl/mem: Trace Memory Module " Ira Weiny
2023-05-09 21:52 ` Dave Jiang
2023-01-18 5:53 ` [PATCH v7 6/8] cxl/test: Add generic mock events Ira Weiny
2023-05-09 22:03 ` Dave Jiang
2023-01-18 5:53 ` [PATCH v7 7/8] cxl/test: Add specific events Ira Weiny
2023-05-09 22:08 ` Dave Jiang [this message]
2023-01-18 5:53 ` [PATCH v7 8/8] cxl/test: Simulate event log overflow Ira Weiny
2023-05-09 22:31 ` Dave Jiang
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