Re: [RFC PATCH 6/6] cxl: Add mce notifier to emit aliased address for extended linear cache

[Dave Jiang <dave.jiang@intel.com>]

On 10/17/24 9:40 AM, Jonathan Cameron wrote:
> On Fri, 27 Sep 2024 07:16:58 -0700
> Dave Jiang <dave.jiang@intel.com> wrote:
> 
>> Below is a setup with extended linear cache configuration with an example
>> layout of of memory region shown below presented as a single memory region
>> consists of 256G memory where there's 128G of DRAM and 128G of CXL memory.
>> The kernel sees a region of total 256G of system memory.
>>
>>               128G DRAM                          128G CXL memory
>> |-----------------------------------|-------------------------------------|
>>
>> Data resides in either DRAM or far memory (FM) with no replication. Hot data
>> is swapped into DRAM by the hardware behind the scenes. When error is detected
>> in one location, it is possible that error also resides in the aliased
>> location. Therefore when a memory location that is flagged by MCE is part of
>> the special region, the aliased memory location needs to be offlined as well.
>>
>> Add an mce notify callback to identify if the MCE address location is part of
>> an extended linear cache region and handle accordingly.
>>
>> Added symbol export to set_mce_nospec() in x86 code in order to call
>> set_mce_nospec() from the CXL MCE notify callback.
> 
> Whilst not commenting on whether any other implementation might exist,
> this code should be written to be arch independent at some level.

I did get a 0-day report on this with mce bits. But with asm/mce.h included, it seems to make other archs happy as well AFAICT.
> 
>>
>> Link: https://lore.kernel.org/linux-cxl/668333b17e4b2_5639294fd@dwillia2-xfh.jf.intel.com.notmuch/
>> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
>