From mboxrd@z Thu Jan 1 00:00:00 1970 From: Nathan Bryant Subject: Re: acpi-20040715: functional regression on ASUS M2N Date: Mon, 02 Aug 2004 12:45:16 -0400 Sender: acpi-devel-admin-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org Message-ID: <410E6F9C.2040904@optonline.net> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Return-path: Errors-To: acpi-devel-admin-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , List-Archive: To: "Georg C. F. Greve" , acpi-devel-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org, shaohua.li-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org List-Id: linux-acpi@vger.kernel.org > I added your suggested patch to > > arch/i386/kernel/i8259.c > > and recompiled. > > Problem persists, no difference I could tell. I don't know why the patch masks out the reserved interrupts. None of the other code that sets ELCR is masking out those bits, and it all works fine. Possibly some chipsets use different edge/level behavior for these, and the save code is forcing them back to edge. Does the problem persist if you go into arch/i386/kernel/i8259.c and change: static void save_ELCR(char *trigger) { /* IRQ 0,1,2,8,13 are marked as reserved */ trigger[0] = inb(0x4d0) & 0xF8; trigger[1] = inb(0x4d1) & 0xDE; } to: static void save_ELCR(char *trigger) { /* IRQ 0,1,2,8,13 are marked as reserved */ trigger[0] = inb(0x4d0); trigger[1] = inb(0x4d1); } ------------------------------------------------------- This SF.Net email is sponsored by OSTG. Have you noticed the changes on Linux.com, ITManagersJournal and NewsForge in the past few weeks? Now, one more big change to announce. We are now OSTG- Open Source Technology Group. Come see the changes on the new OSTG site. www.ostg.com