Re: [PATHC] Relaxed syntax for the processor PBLK length

[Herman Sheremetyev <herman-6MNMYbGzEYJWk0Htik3J/w@public.gmane.org>]

A length other than 6 used to disable PBLK may also indicate that C 
states are implemented using _CST methods instead of the Processor 
structure.  At least that's how it is on Asus M6N series, PBLK length is 
set to 7, and there are some other clues in the FADT latency settings to 
indicate that the BIOS writers didn't want this info used.

-Herman

Bruno Ducrot wrote:
> On Mon, Jan 31, 2005 at 04:11:59PM +0100, Eric Piel wrote:
> 
>>Why? Actually this patch is especially designed to allow C3 state to be 
>>used on my computer. This works for more than 6 months without any 
>>appearent problem, is there anything I'm not aware of?
> 
> 
> I thought some BIOS devellopers wanted to use a size for the
> pblk of 5 just to not allow C3 (which correspond to the sixth io
> register).
> 
> I'm not alone to think this.
> 
> Nate: FreeBSD allow only C2 in this case.  What do you think about this
> report?
> Do you have an example of some kind of malfunction when enabling C3?
> 


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