From mboxrd@z Thu Jan  1 00:00:00 1970
From: "H. Peter Anvin" <hpa@zytor.com>
Subject: Re: [PATCH 10/10] x86, ACPI: default to reboot via ACPI (again)
Date: Wed, 12 Nov 2008 20:34:11 -0800
Message-ID: <491BAE43.5080309@zytor.com>
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To: "Eric W. Biederman" <ebiederm@xmission.com>
Cc: Zhao Yakui <yakui.zhao@intel.com>, Avi Kivity <avi@redhat.com>, Ingo Molnar <mingo@elte.hu>, Len Brown <lenb@kernel.org>, Stephen Rothwell <sfr@canb.auug.org.au>, Andrew Morton <akpm@linux-foundation.org>, Matthew Garrett <mjg@redhat.com>, Andrey Borzenkov <arvidjaar@mail.ru>, "linux-acpi@vger.kernel.org" <linux-acpi@vger.kernel.org>, "Brown, Len" <len.brown@intel.com>, Thomas Gleixner <tglx@linutronix.de>, Eduardo Habkost <ehabkost@redhat.com>

Eric W. Biederman wrote:
>=20
> Looking at the coreboot source.  It is indeed defined for Nvidia, SIS=
,
> AMD and several others.
>=20
> A lot of boards use:
> outb(0x02, 0xcf9);
> outb(0x06, 0xcf9);
>=20
> Instead of just writing a plain 6.   I think at least on some machine=
s
> there is a requirement for a low to hight transition.
>=20

That is correct; that is what my patch has, with a 50 =C2=B5s delay in
between (I also don't touch the ~6 bits.)

>=20
> Right.  The only scary question is will a motherboard hang if you wri=
te
> to 0xcf9.  If we don't know of an example where writing to 0xcf9 will=
 prevent
> us from getting to the next reset method then adding a generic 0xcf9 =
is
> safe.
>=20

It would be highly surprising, except possibly on pre-PCI systems, whic=
h
is why my patch skips CF9 if the standard PCI ports are not detected.
Although CF9 isn't defined in the PCI spec, it falls in the PCI
configuration port range.

	-hpa
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