* Working DSDT+SSDT, what's next?
@ 2010-04-16 18:42 pat-lkml
2010-04-19 4:47 ` Pat Erley
0 siblings, 1 reply; 3+ messages in thread
From: pat-lkml @ 2010-04-16 18:42 UTC (permalink / raw)
To: linux-acpi
Ok, first time poster, long time reader.
I have a Clevo D900T mobo based laptop. These were only ever produced
with p4 5xx series chips, but the chipset (ICH6) supports the 6xx series.
Because it was never produced with a 6xx cpu, a bios was never released
that supported things like EIST or EM64T. EM64T worked fine, out of the
box. EIST did not (due to no SSDT tables with PSS/PCT/PPC methods). I was
able to get EIST working with a hacked-up DSDT, but I'm curious if I'm
doing everything I should.
Intel CPU Spec: http://processorfinder.intel.com/details.aspx?sSpec=SL8Q7
Intel Data Sheet:
http://download.intel.com/design/Pentium4/datashts/303128.pdf
Right now, I just have 2 C States, for 3.0Ghz and 2.8Ghz. It's my
understanding that these are the only speeds EIST can do in this CPU.
now, the questions:
1. Is there something I should be doing with a _CSD type entry in my
CPU{0,1} entries to signify that they're HT?
2. How can I verify that EIST is actually working?
3. How do I determine VID values?
a. I've just lowered VID 1 by 1, loading the system until it became
unstable, at which point I added 1 and called it good
b. Is there any advantage to multiple VID's with 1 VID? IE:
3ghz@1.45V, 3Ghz@1.25V
4. in the PSS table, the first entry (3000,2800 in my case), are those
just for show?
5. Are there additional features the CPU supports that, due to bios
limitation, I should enable this way (C1E?)
outline of what I've done: http://pat.erley.org/Other/P4EISTSSDT
Pat Erley
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: Working DSDT+SSDT, what's next?
2010-04-16 18:42 Working DSDT+SSDT, what's next? pat-lkml
@ 2010-04-19 4:47 ` Pat Erley
2010-05-06 6:00 ` Len Brown
0 siblings, 1 reply; 3+ messages in thread
From: Pat Erley @ 2010-04-19 4:47 UTC (permalink / raw)
To: linux-acpi
Ok, I've continued learning, more info injected below:
On 04/16/10 14:42, pat-lkml@erley.org wrote:
> Ok, first time poster, long time reader.
>
> I have a Clevo D900T mobo based laptop. These were only ever produced
> with p4 5xx series chips, but the chipset (ICH6) supports the 6xx series.
> Because it was never produced with a 6xx cpu, a bios was never released
> that supported things like EIST or EM64T. EM64T worked fine, out of the
> box. EIST did not (due to no SSDT tables with PSS/PCT/PPC methods). I was
> able to get EIST working with a hacked-up DSDT, but I'm curious if I'm
> doing everything I should.
>
> Intel CPU Spec: http://processorfinder.intel.com/details.aspx?sSpec=SL8Q7
> Intel Data Sheet:
> http://download.intel.com/design/Pentium4/datashts/303128.pdf
>
> Right now, I just have 2 C States, for 3.0Ghz and 2.8Ghz. It's my
> understanding that these are the only speeds EIST can do in this CPU.
>
> now, the questions:
>
> 1. Is there something I should be doing with a _CSD type entry in my
> CPU{0,1} entries to signify that they're HT?
Yep, I needed to add a pair of _CSD entries. EIST is now adjusting speeds correctly!
> 3. How do I determine VID values?
> a. I've just lowered VID 1 by 1, loading the system until it became
> unstable, at which point I added 1 and called it good
> b. Is there any advantage to multiple VID's with 1 VID? IE:
> 3ghz@1.45V, 3Ghz@1.25V
People in linux-pch have helped me here
> 4. in the PSS table, the first entry (3000,2800 in my case), are those
> just for show?
Still don't have an answer here.
> 5. Are there additional features the CPU supports that, due to bios
> limitation, I should enable this way (C1E?)
Ok, I now now I need to come up with a _CST table (unless one of the other tables is doing this...) to enable C-States, and C1E in particular... Anyone have any pointers on where to start on this? All of the info I seem to be able to find are for C2Q and newer CPUs, not older P4s like what I have.
> outline of what I've done: http://pat.erley.org/Other/P4EISTSSDT
>
> Pat Erley
Pat Erley
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: Working DSDT+SSDT, what's next?
2010-04-19 4:47 ` Pat Erley
@ 2010-05-06 6:00 ` Len Brown
0 siblings, 0 replies; 3+ messages in thread
From: Len Brown @ 2010-05-06 6:00 UTC (permalink / raw)
To: Pat Erley; +Cc: linux-acpi
On Mon, 19 Apr 2010, Pat Erley wrote:
> Ok, I've continued learning, more info injected below:
>
> On 04/16/10 14:42, pat-lkml@erley.org wrote:
> > Ok, first time poster, long time reader.
> >
> > I have a Clevo D900T mobo based laptop. These were only ever produced
> > with p4 5xx series chips, but the chipset (ICH6) supports the 6xx series.
> > Because it was never produced with a 6xx cpu, a bios was never released
> > that supported things like EIST or EM64T. EM64T worked fine, out of the
> > box. EIST did not (due to no SSDT tables with PSS/PCT/PPC methods). I was
> > able to get EIST working with a hacked-up DSDT, but I'm curious if I'm
> > doing everything I should.
> >
> > Intel CPU Spec: http://processorfinder.intel.com/details.aspx?sSpec=SL8Q7
> > Intel Data Sheet:
> > http://download.intel.com/design/Pentium4/datashts/303128.pdf
> >
> > Right now, I just have 2 C States, for 3.0Ghz and 2.8Ghz. It's my
> > understanding that these are the only speeds EIST can do in this CPU.
Those are P-states, not C-states.
> > now, the questions:
> >
> > 1. Is there something I should be doing with a _CSD type entry in my
> > CPU{0,1} entries to signify that they're HT?
>
> Yep, I needed to add a pair of _CSD entries. EIST is now adjusting speeds correctly!
That's funny, P-states and EIST have nothing to do with _CSD.
> > 3. How do I determine VID values?
> > a. I've just lowered VID 1 by 1, loading the system until it became
> > unstable, at which point I added 1 and called it good
> > b. Is there any advantage to multiple VID's with 1 VID? IE:
> > 3ghz@1.45V, 3Ghz@1.25V
>
> People in linux-pch have helped me here
you're on very thin ice here.
In theory, the BIOS is supposed to match the capabilities of the
motherboard. The BIOS may not expose something on the motherboard
because it may be broken.
> > 4. in the PSS table, the first entry (3000,2800 in my case), are those
> > just for show?
>
> Still don't have an answer here.
>
> > 5. Are there additional features the CPU supports that, due to bios
> > limitation, I should enable this way (C1E?)
C1 and C1E are identical from an OS point of view.
> Ok, I now now I need to come up with a _CST table (unless one of the other tables is doing this...)
> to enable C-States, and C1E in particular...
> Anyone have any pointers on where to start on this?
> All of the info I seem to be able to find are for C2Q and newer CPUs,
> not older P4s like what I have.
>
> > outline of what I've done: http://pat.erley.org/Other/P4EISTSSDT
Honestly, Pat, if you want to slow down a P4,
just use p4clockmod until you can get more capable hardware.
-Len Brown, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 3+ messages in thread
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2010-04-16 18:42 Working DSDT+SSDT, what's next? pat-lkml
2010-04-19 4:47 ` Pat Erley
2010-05-06 6:00 ` Len Brown
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