From: "Zhang, Rui" <rui.zhang@intel.com>
To: "Mehta, Sohil" <sohil.mehta@intel.com>,
"Luck, Tony" <tony.luck@intel.com>,
"x86@kernel.org" <x86@kernel.org>,
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Subject: Re: [PATCH v2 06/17] cpufreq: Fix the efficient idle check for Intel extended Families
Date: Wed, 12 Feb 2025 05:35:05 +0000 [thread overview]
Message-ID: <56eb1f8bda3932632cc0b17dde053f77fe7f3f89.camel@intel.com> (raw)
In-Reply-To: <20250211194407.2577252-7-sohil.mehta@intel.com>
On Tue, 2025-02-11 at 19:43 +0000, Sohil Mehta wrote:
> IO time is considered as busy by default for modern Intel processors.
> However the check doesn't include the upcoming Family 18 and 19
> processors. Also, Arjan van de Ven says the current nature of the
> check
> was mainly due to lack of testing on old systems. He suggests
> considering all Intel processors as having efficient idle.
>
> Extend the IO busy classification to all Intel processors starting
> with
> Family 6.
>
> Signed-off-by: Sohil Mehta <sohil.mehta@intel.com>
>
> ---
>
> v2: Improve commit message and code comments.
>
> ---
> drivers/cpufreq/cpufreq_ondemand.c | 15 +++++++++------
> 1 file changed, 9 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/cpufreq/cpufreq_ondemand.c
> b/drivers/cpufreq/cpufreq_ondemand.c
> index a7c38b8b3e78..b13f197707f4 100644
> --- a/drivers/cpufreq/cpufreq_ondemand.c
> +++ b/drivers/cpufreq/cpufreq_ondemand.c
> @@ -15,6 +15,10 @@
> #include <linux/tick.h>
> #include <linux/sched/cpufreq.h>
>
> +#ifdef CONFIG_X86
> +#include <asm/cpu_device_id.h>
> +#endif
> +
> #include "cpufreq_ondemand.h"
>
> /* On-demand governor macros */
> @@ -32,21 +36,20 @@ static unsigned int default_powersave_bias;
> /*
> * Not all CPUs want IO time to be accounted as busy; this depends
> on how
> * efficient idling at a higher frequency/voltage is.
> - * Pavel Machek says this is not so for various generations of AMD
> and old
> - * Intel systems.
> + * Pavel Machek says this is not so for various generations of AMD.
> * Mike Chan (android.com) claims this is also not true for ARM.
> - * Because of this, whitelist specific known (series) of CPUs by
> default, and
> + * Because of this, select known series of CPUs by default, and
> * leave all others up to the user.
> */
> static int should_io_be_busy(void)
> {
> #if defined(CONFIG_X86)
> /*
> - * For Intel, Core 2 (model 15) and later have an efficient
> idle.
> + * Starting with Family 6 consider all Intel CPUs to have an
> + * efficient idle.
> */
> if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
> - boot_cpu_data.x86 == 6 &&
> - boot_cpu_data.x86_model >= 15)
> + boot_cpu_data.x86_vfm >= INTEL_PENTIUM_PRO)
This is "Starting from P4" rather than "Starting from Family 6", right?
thanks,
rui
> return 1;
> #endif
> return 0;
next prev parent reply other threads:[~2025-02-12 5:35 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-11 19:43 [PATCH v2 00/17] Prepare for new Intel Family numbers Sohil Mehta
2025-02-11 19:43 ` [PATCH v2 01/17] x86/smpboot: Remove confusing quirk usage in INIT delay Sohil Mehta
2025-02-11 19:43 ` [PATCH v2 02/17] x86/smpboot: Fix INIT delay optimization for extended Intel Families Sohil Mehta
2025-02-11 20:10 ` Dave Hansen
2025-02-11 20:20 ` Sohil Mehta
2025-02-11 19:43 ` [PATCH v2 03/17] x86/apic: Fix 32-bit APIC initialization " Sohil Mehta
2025-02-11 19:43 ` [PATCH v2 04/17] x86/cpu/intel: Fix the movsl alignment preference for extended Families Sohil Mehta
2025-02-11 20:26 ` Dave Hansen
2025-02-11 21:45 ` David Laight
2025-02-11 19:43 ` [PATCH v2 05/17] x86/cpu/intel: Fix page copy performance " Sohil Mehta
2025-02-11 20:53 ` Dave Hansen
2025-02-12 0:54 ` Andrew Cooper
2025-02-12 21:19 ` Sohil Mehta
2025-02-13 23:02 ` Andrew Cooper
2025-02-14 0:29 ` Sohil Mehta
2025-02-11 19:43 ` [PATCH v2 06/17] cpufreq: Fix the efficient idle check for Intel " Sohil Mehta
2025-02-12 5:35 ` Zhang, Rui [this message]
2025-02-13 18:49 ` Sohil Mehta
2025-02-14 2:03 ` Zhang, Rui
2025-02-11 19:43 ` [PATCH v2 07/17] hwmon: Fix Intel Family-model checks to include " Sohil Mehta
2025-02-11 20:58 ` Dave Hansen
2025-02-11 21:38 ` Sohil Mehta
2025-02-12 13:43 ` Zhang, Rui
2025-02-12 16:57 ` Dave Hansen
2025-02-14 2:23 ` Zhang, Rui
2025-02-12 13:10 ` Zhang, Rui
2025-02-11 19:43 ` [PATCH v2 08/17] x86/microcode: Update the Intel processor flag scan check Sohil Mehta
2025-02-11 21:00 ` Dave Hansen
2025-02-11 19:43 ` [PATCH v2 09/17] x86/mtrr: Modify a x86_model check to an Intel VFM check Sohil Mehta
2025-02-11 21:00 ` Dave Hansen
2025-02-11 19:44 ` [PATCH v2 10/17] x86/cpu/intel: Replace early Family 6 checks with VFM ones Sohil Mehta
2025-02-11 21:03 ` Dave Hansen
2025-02-11 19:44 ` [PATCH v2 11/17] x86/cpu/intel: Replace Family 15 " Sohil Mehta
2025-02-11 21:03 ` Dave Hansen
2025-02-11 19:44 ` [PATCH v2 12/17] x86/cpu/intel: Replace Family 5 model " Sohil Mehta
2025-02-11 21:06 ` Dave Hansen
2025-02-11 19:44 ` [PATCH v2 13/17] x86/pat: Replace Intel x86_model " Sohil Mehta
2025-02-11 21:09 ` Dave Hansen
2025-02-11 21:42 ` Sohil Mehta
2025-02-11 19:44 ` [PATCH v2 14/17] x86/acpi/cstate: Improve Intel Family model checks Sohil Mehta
2025-02-11 21:20 ` Dave Hansen
2025-02-11 19:44 ` [PATCH v2 15/17] x86/cpu/intel: Bound the non-architectural constant_tsc " Sohil Mehta
2025-02-11 21:41 ` Dave Hansen
2025-02-12 0:45 ` Sohil Mehta
2025-02-11 19:44 ` [PATCH v2 16/17] perf/x86: Simplify P6 PMU initialization Sohil Mehta
2025-02-11 19:44 ` [PATCH v2 17/17] perf/x86/p4: Replace Pentium 4 model checks with VFM ones Sohil Mehta
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