From: James Morse <james.morse@arm.com>
To: Tyler Baicar <tbaicar@codeaurora.org>
Cc: linux-efi@vger.kernel.org, kvm@vger.kernel.org,
matt@codeblueprint.co.uk, catalin.marinas@arm.com,
will.deacon@arm.com, robert.moore@intel.com,
paul.gortmaker@windriver.com, lv.zheng@intel.com,
kvmarm@lists.cs.columbia.edu, fu.wei@linaro.org,
zjzhang@codeaurora.org, linux@armlinux.org.uk,
linux-acpi@vger.kernel.org, eun.taik.lee@samsung.com,
shijie.huang@arm.com, labbott@redhat.com, lenb@kernel.org,
harba@codeaurora.org, john.garry@huawei.com,
marc.zyngier@arm.com, punit.agrawal@arm.com, rostedt@goodmis.org,
nkaje@codeaurora.org, sandeepa.s.prabhu@gmail.com,
linux-arm-kernel@lists.infradead.org, devel@acpica.org,
rjw@rjwysocki.net, rruigrok@codeaurora.org,
linux-kernel@vger.kernel.org, astone@redhat.com,
hanjun.guo@linaro.org, pbonzini@redhat.com,
akpm@linux-foundation.org, bristot@redhat.com,
shiju.jose@huawei.com
Subject: Re: [PATCH V8 04/10] arm64: exception: handle Synchronous External Abort
Date: Fri, 03 Feb 2017 15:59:33 +0000 [thread overview]
Message-ID: <5894A8E5.6000803@arm.com> (raw)
In-Reply-To: <1485969413-23577-5-git-send-email-tbaicar@codeaurora.org>
Hi Tyler,
On 01/02/17 17:16, Tyler Baicar wrote:
> SEA exceptions are often caused by an uncorrected hardware
> error, and are handled when data abort and instruction abort
> exception classes have specific values for their Fault Status
> Code.
> When SEA occurs, before killing the process, report the error
> in the kernel logs.
> Update fault_info[] with specific SEA faults so that the
> new SEA handler is used.
> diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c
> index 156169c..9ae7e65 100644
> --- a/arch/arm64/mm/fault.c
> +++ b/arch/arm64/mm/fault.c
> @@ -487,6 +487,31 @@ static int do_bad(unsigned long addr, unsigned int esr, struct pt_regs *regs)
> return 1;
> }
>
> +#define SEA_FnV_MASK 0x00000400
There are a glut of ESR_ELx_ macros in arch/arm64/include/asm/esr.h, could this
be fitted in there in a similar format?
--- a/arch/arm64/include/asm/esr.h
+++ b/arch/arm64/include/asm/esr.h
@@ -83,6 +83,7 @@
#define ESR_ELx_WNR (UL(1) << 6)
/* Shared ISS field definitions for Data/Instruction aborts */
+#define ESR_ELx_FnV (UL(1) << 10)
#define ESR_ELx_EA (UL(1) << 9)
#define ESR_ELx_S1PTW (UL(1) << 7)
> +
> +/*
> + * This abort handler deals with Synchronous External Abort.
> + * It calls notifiers, and then returns "fault".
> + */
> +static int do_sea(unsigned long addr, unsigned int esr, struct pt_regs *regs)
> +{
> + struct siginfo info;
> +
> + pr_err("Synchronous External Abort: %s (0x%08x) at 0x%016lx\n",
> + fault_name(esr), esr, addr);
> +
> + info.si_signo = SIGBUS;
> + info.si_errno = 0;
> + info.si_code = 0;
> + if (esr & SEA_FnV_MASK)
> + info.si_addr = 0;
> + else
> + info.si_addr = (void __user *)addr;
> + arm64_notify_die("", regs, &info, esr);
> +
> + return 0;
> +}
> +
> static const struct fault_info {
> int (*fn)(unsigned long addr, unsigned int esr, struct pt_regs *regs);
> int sig;
> @@ -509,22 +534,22 @@ static int do_bad(unsigned long addr, unsigned int esr, struct pt_regs *regs)
> { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 1 permission fault" },
> { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 2 permission fault" },
> { do_page_fault, SIGSEGV, SEGV_ACCERR, "level 3 permission fault" },
> - { do_bad, SIGBUS, 0, "synchronous external abort" },
> + { do_sea, SIGBUS, 0, "synchronous external abort" },
This will print:
> Synchronous External Abort: synchronous external abort
It looks odd, but I can't think of anything better to put there.
> { do_bad, SIGBUS, 0, "unknown 17" },
> { do_bad, SIGBUS, 0, "unknown 18" },
> { do_bad, SIGBUS, 0, "unknown 19" },
> - { do_bad, SIGBUS, 0, "synchronous external abort (translation table walk)" },
> - { do_bad, SIGBUS, 0, "synchronous external abort (translation table walk)" },
> - { do_bad, SIGBUS, 0, "synchronous external abort (translation table walk)" },
> - { do_bad, SIGBUS, 0, "synchronous external abort (translation table walk)" },
> - { do_bad, SIGBUS, 0, "synchronous parity error" },
> + { do_sea, SIGBUS, 0, "level 0 (translation table walk)" },
> + { do_sea, SIGBUS, 0, "level 1 (translation table walk)" },
> + { do_sea, SIGBUS, 0, "level 2 (translation table walk)" },
> + { do_sea, SIGBUS, 0, "level 3 (translation table walk)" },
> + { do_sea, SIGBUS, 0, "synchronous parity or ECC error" },
> { do_bad, SIGBUS, 0, "unknown 25" },
> { do_bad, SIGBUS, 0, "unknown 26" },
> { do_bad, SIGBUS, 0, "unknown 27" },
> - { do_bad, SIGBUS, 0, "synchronous parity error (translation table walk)" },
> - { do_bad, SIGBUS, 0, "synchronous parity error (translation table walk)" },
> - { do_bad, SIGBUS, 0, "synchronous parity error (translation table walk)" },
> - { do_bad, SIGBUS, 0, "synchronous parity error (translation table walk)" },
> + { do_sea, SIGBUS, 0, "level 0 synchronous parity error (translation table walk)" },
> + { do_sea, SIGBUS, 0, "level 1 synchronous parity error (translation table walk)" },
> + { do_sea, SIGBUS, 0, "level 2 synchronous parity error (translation table walk)" },
> + { do_sea, SIGBUS, 0, "level 3 synchronous parity error (translation table walk)" },
> { do_bad, SIGBUS, 0, "unknown 32" },
> { do_alignment_fault, SIGBUS, BUS_ADRALN, "alignment fault" },
> { do_bad, SIGBUS, 0, "unknown 34" },
>
With the ESR_ELx_FnV change above,
Reviewed-by: James Morse <james.morse@arm.com>
Thanks,
James
next prev parent reply other threads:[~2017-02-03 15:59 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-01 17:16 [PATCH V8 00/10] Add UEFI 2.6 and ACPI 6.1 updates for RAS on ARM64 Tyler Baicar
2017-02-01 17:16 ` [PATCH V8 01/10] acpi: apei: read ack upon ghes record consumption Tyler Baicar
2017-02-01 17:16 ` [PATCH V8 02/10] ras: acpi/apei: cper: generic error data entry v3 per ACPI 6.1 Tyler Baicar
2017-02-01 17:16 ` [PATCH V8 03/10] efi: parse ARM processor error Tyler Baicar
2017-02-01 17:16 ` [PATCH V8 04/10] arm64: exception: handle Synchronous External Abort Tyler Baicar
2017-02-03 15:59 ` James Morse [this message]
2017-02-03 20:24 ` Baicar, Tyler
2017-02-01 17:16 ` [PATCH V8 05/10] acpi: apei: handle SEA notification type for ARMv8 Tyler Baicar
[not found] ` <1485969413-23577-6-git-send-email-tbaicar-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2017-02-01 22:26 ` kbuild test robot
2017-02-03 16:00 ` James Morse
2017-02-03 20:38 ` Baicar, Tyler
2017-02-15 6:24 ` Zhengqiang
2017-02-15 14:58 ` Baicar, Tyler
2017-02-01 17:16 ` [PATCH V8 06/10] acpi: apei: panic OS with fatal error status block Tyler Baicar
2017-02-09 10:48 ` James Morse
[not found] ` <589C490A.9080109-5wv7dgnIgG8@public.gmane.org>
2017-02-13 22:45 ` Baicar, Tyler
[not found] ` <5b06372d-e389-5157-ccb4-a7b023990d4d-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2017-02-15 12:13 ` James Morse
[not found] ` <58A445D5.7030501-5wv7dgnIgG8@public.gmane.org>
2017-02-15 17:07 ` Baicar, Tyler
2017-02-01 17:16 ` [PATCH V8 07/10] efi: print unrecognized CPER section Tyler Baicar
2017-02-01 17:16 ` [PATCH V8 08/10] ras: acpi / apei: generate trace event for " Tyler Baicar
2017-02-01 23:20 ` kbuild test robot
2017-02-15 15:52 ` Steven Rostedt
2017-02-15 16:54 ` Baicar, Tyler
2017-02-15 17:03 ` Steven Rostedt
2017-02-15 17:06 ` Baicar, Tyler
2017-02-01 17:16 ` [PATCH V8 09/10] trace, ras: add ARM processor error trace event Tyler Baicar
2017-02-02 2:34 ` kbuild test robot
2017-02-02 3:15 ` Steven Rostedt
2017-02-03 20:18 ` Baicar, Tyler
2017-02-01 17:16 ` [PATCH V8 10/10] arm/arm64: KVM: add guest SEA support Tyler Baicar
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