From: Dan Williams <dan.j.williams@intel.com>
To: Dave Jiang <dave.jiang@intel.com>, <linux-cxl@vger.kernel.org>,
<linux-acpi@vger.kernel.org>
Cc: <dan.j.williams@intel.com>, <ira.weiny@intel.com>,
<vishal.l.verma@intel.com>, <alison.schofield@intel.com>,
<rafael@kernel.org>, <lukas@wunner.de>,
<Jonathan.Cameron@huawei.com>
Subject: RE: [PATCH v4 07/23] cxl: Add callback to parse the SSLBIS subtable from CDAT
Date: Mon, 24 Apr 2023 16:38:59 -0700 [thread overview]
Message-ID: <64471313421f7_1b66294d5@dwillia2-xfh.jf.intel.com.notmuch> (raw)
In-Reply-To: <168193570345.1178687.2383268813534307968.stgit@djiang5-mobl3>
Dave Jiang wrote:
> Provide a callback to parse the Switched Scoped Latency and Bandwidth
> Information Structure (DSLBIS) in the CDAT structures. The SSLBIS
> contains the bandwidth and latency information that's tied to the
> CLX switch that the data table has been read from. The extracted
s/CLX/CXL/
> values are indexed by the downstream port id.
For other readers of this patch it might be worth mentioning that this
corresponds to 'struct cxl_dport::portid'.
> It is possible the downstream port id is 0xffff which is a wildcard
> value for any port id.
>
> Coherent Device Attribute Table 1.03 2.1 Switched Scoped Latency
> and Bandwidth Information Structure (DSLBIS)
>
> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
>
> ---
> v3:
> - Add spec section in commit header (Alison)
> - Move CDAT parse to cxl_switch_port_probe()
> - Use 'struct node_hmem_attrs'
> ---
> drivers/cxl/core/cdat.c | 76 +++++++++++++++++++++++++++++++++++++++++++++++
> drivers/cxl/core/port.c | 5 +++
> drivers/cxl/cxl.h | 1 +
> drivers/cxl/cxlpci.h | 20 ++++++++++++
> drivers/cxl/port.c | 14 ++++++++-
> 5 files changed, 115 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/cxl/core/cdat.c b/drivers/cxl/core/cdat.c
> index e8b9bb99dfdf..ec3420dddf27 100644
> --- a/drivers/cxl/core/cdat.c
> +++ b/drivers/cxl/core/cdat.c
> @@ -192,3 +192,79 @@ int cxl_dslbis_parse_entry(struct cdat_entry_header *header, void *arg)
> return 0;
> }
> EXPORT_SYMBOL_NS_GPL(cxl_dslbis_parse_entry, CXL);
> +
> +int cxl_sslbis_parse_entry(struct cdat_entry_header *header, void *arg)
> +{
> + struct cdat_sslbis *sslbis = (struct cdat_sslbis *)header;
> + struct xarray *sslbis_xa = arg;
> + int remain, entries, i;
> +
> + remain = sslbis->hdr.length - sizeof(*sslbis);
> + if (!remain || remain % sizeof(struct sslbis_sslbe)) {
> + pr_warn("Malformed SSLBIS table length: (%u)\n",
> + sslbis->hdr.length);
> + return -EINVAL;
> + }
> +
> + /* Unrecognized data type, we can skip */
> + if (sslbis->data_type >= HMAT_SLLBIS_DATA_TYPE_MAX)
> + return 0;
> +
> + entries = remain / sizeof(*sslbis);
> +
> + for (i = 0; i < entries; i++) {
> + struct sslbis_sslbe *sslbe = &sslbis->sslbe[i];
> + u16 x = le16_to_cpu(sslbe->port_x_id);
> + u16 y = le16_to_cpu(sslbe->port_y_id);
> + struct node_hmem_attrs *hmem_attrs;
The more "node_hmem_attrs" get reused the more it sticks out as no
longer a good name. There's no Linux "nodes" to consider in this code,
no hmem since this is switch path and not a memory node, and no sysfs
attributes (which are typically named with "_attrs"). This data
structure is just a container for passing a tuple of r/w-latency and
r/w-bandwidth numbers. It's a performance coordinate that just happens
to get reused by the hmem sysfs nodes and now CXL cdat. Perhaps 'struct
access_coordinate'?
That would also make this code more readable:
void node_set_perf_attrs(unsigned int nid, struct node_hmem_attrs *hmem_attrs,
unsigned access);
...vs:
void node_set_perf_attrs(unsigned int nid, struct access_coordinate *coord,
unsigned access);
...at least that seems more readable to me.
> + u16 dsp_id;
> + u64 val;
> + int rc;
> +
> + switch (x) {
> + case SSLBIS_US_PORT:
> + dsp_id = y;
> + break;
> + case SSLBIS_ANY_PORT:
> + switch (y) {
> + case SSLBIS_US_PORT:
> + dsp_id = x;
> + break;
> + case SSLBIS_ANY_PORT:
> + dsp_id = SSLBIS_ANY_PORT;
> + break;
> + default:
> + dsp_id = y;
> + break;
> + }
> + break;
> + default:
> + dsp_id = x;
> + break;
> + }
> +
> + hmem_attrs = xa_load(sslbis_xa, dsp_id);
> + if (xa_is_err(hmem_attrs))
> + return xa_err(hmem_attrs);
> + if (!hmem_attrs) {
> + hmem_attrs = kzalloc(sizeof(*hmem_attrs), GFP_KERNEL);
> + if (!hmem_attrs)
> + return -ENOMEM;
> + }
> +
> + rc = check_mul_overflow(le64_to_cpu(sslbis->entry_base_unit),
> + le16_to_cpu(sslbe->value), &val);
> + if (unlikely(rc))
> + pr_warn("SSLBIS value overflowed!\n");
> +
> + cxl_hmem_attrs_set(hmem_attrs, sslbis->data_type, val);
> + rc = xa_insert(sslbis_xa, dsp_id, hmem_attrs, GFP_KERNEL);
I'm confused why an xarray is needed. If the sslbis indicates the access
parameters from the upstream port to the downstream port, just record
that access_coordinate and point each downstream port to the same
coordinate. Why keep an xarray full of these around?
In other words just add 'struct access_coordinate' to 'struct cxl_dport'
rather maintaining this parallel array of per-downstream port data.
When / if p2p support comes along then we can worry about dport-to-dport
performance, but for this patchset those sslbis entries are 'don't care'.
> + if (rc < 0 && rc != -EBUSY) {
> + kfree(hmem_attrs);
> + return rc;
> + }
> + }
> +
> + return 0;
> +}
> +EXPORT_SYMBOL_NS_GPL(cxl_sslbis_parse_entry, CXL);
next prev parent reply other threads:[~2023-04-24 23:39 UTC|newest]
Thread overview: 70+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-19 20:21 [PATCH v4 00/23] cxl: Add support for QTG ID retrieval for CXL subsystem Dave Jiang
2023-04-19 20:21 ` [PATCH v4 01/23] cxl: Export QTG ids from CFMWS to sysfs Dave Jiang
2023-04-20 8:51 ` Jonathan Cameron
2023-04-20 20:53 ` Dave Jiang
2023-04-24 21:46 ` Dan Williams
2023-04-26 23:14 ` Dave Jiang
2023-04-19 20:21 ` [PATCH v4 02/23] cxl: Add checksum verification to CDAT from CXL Dave Jiang
2023-04-20 8:55 ` Jonathan Cameron
2023-04-24 22:01 ` Dan Williams
2023-04-26 23:24 ` Dave Jiang
2023-04-19 20:21 ` [PATCH v4 03/23] cxl: Add support for reading CXL switch CDAT table Dave Jiang
2023-04-20 9:25 ` Jonathan Cameron
2023-04-24 22:08 ` Dan Williams
2023-04-27 15:55 ` Dave Jiang
2023-04-19 20:21 ` [PATCH v4 04/23] cxl: Add common helpers for cdat parsing Dave Jiang
2023-04-20 9:41 ` Jonathan Cameron
2023-04-20 21:05 ` Dave Jiang
2023-04-21 16:06 ` Jonathan Cameron
2023-04-21 16:12 ` Dave Jiang
2023-04-24 22:33 ` Dan Williams
2023-04-25 16:00 ` Dave Jiang
2023-04-27 0:09 ` Dan Williams
2023-04-19 20:21 ` [PATCH v4 05/23] cxl: Add callback to parse the DSMAS subtables from CDAT Dave Jiang
2023-04-20 11:33 ` Jonathan Cameron
2023-04-20 11:35 ` Jonathan Cameron
2023-04-20 23:25 ` Dave Jiang
2023-04-24 22:38 ` Dan Williams
2023-04-26 3:44 ` Li, Ming
2023-04-26 18:27 ` Dave Jiang
2023-04-19 20:21 ` [PATCH v4 06/23] cxl: Add callback to parse the DSLBIS subtable " Dave Jiang
2023-04-20 11:40 ` Jonathan Cameron
2023-04-20 23:25 ` Dave Jiang
2023-04-24 22:46 ` Dan Williams
2023-04-24 22:59 ` Dave Jiang
2023-04-19 20:21 ` [PATCH v4 07/23] cxl: Add callback to parse the SSLBIS " Dave Jiang
2023-04-20 11:50 ` Jonathan Cameron
2023-04-24 23:38 ` Dan Williams [this message]
2023-04-19 20:21 ` [PATCH v4 08/23] cxl: Add support for _DSM Function for retrieving QTG ID Dave Jiang
2023-04-20 12:00 ` Jonathan Cameron
2023-04-21 0:11 ` Dave Jiang
2023-04-21 16:07 ` Jonathan Cameron
2023-04-25 0:12 ` Dan Williams
2023-04-19 20:21 ` [PATCH v4 09/23] cxl: Add helper function to retrieve ACPI handle of CXL root device Dave Jiang
2023-04-20 12:06 ` Jonathan Cameron
2023-04-21 23:24 ` Dave Jiang
2023-04-25 0:18 ` Dan Williams
2023-04-19 20:22 ` [PATCH v4 10/23] cxl: Add helpers to calculate pci latency for the CXL device Dave Jiang
2023-04-20 12:15 ` Jonathan Cameron
2023-04-25 0:30 ` Dan Williams
2023-05-01 16:29 ` Dave Jiang
2023-04-19 20:22 ` [PATCH v4 11/23] cxl: Add helper function that calculates QoS values for switches Dave Jiang
2023-04-20 12:26 ` Jonathan Cameron
2023-04-24 17:09 ` Dave Jiang
2023-04-24 17:31 ` Dave Jiang
2023-04-24 21:59 ` Jonathan Cameron
2023-04-25 0:33 ` Dan Williams
2023-04-19 20:22 ` [PATCH v4 12/23] cxl: Add helper function that calculate QoS values for PCI path Dave Jiang
2023-04-20 12:32 ` Jonathan Cameron
2023-04-25 0:45 ` Dan Williams
2023-04-19 20:22 ` [PATCH v4 13/23] ACPI: NUMA: Create enum for memory_target hmem_attrs indexing Dave Jiang
2023-04-19 20:22 ` [PATCH v4 14/23] ACPI: NUMA: Add genport target allocation to the HMAT parsing Dave Jiang
2023-04-19 20:22 ` [PATCH v4 15/23] ACPI: NUMA: Add setting of generic port locality attributes Dave Jiang
2023-04-19 20:22 ` [PATCH v4 16/23] ACPI: NUMA: Add helper function to retrieve the performance attributes Dave Jiang
2023-04-19 20:22 ` [PATCH v4 17/23] cxl: Add helper function to retrieve generic port QoS Dave Jiang
2023-04-19 20:22 ` [PATCH v4 18/23] cxl: Add latency and bandwidth calculations for the CXL path Dave Jiang
2023-04-19 20:22 ` [PATCH v4 19/23] cxl: Wait Memory_Info_Valid before access memory related info Dave Jiang
2023-04-19 20:23 ` [PATCH v4 20/23] cxl: Move identify and partition query from pci probe to port probe Dave Jiang
2023-04-19 20:23 ` [PATCH v4 21/23] cxl: Store QTG IDs and related info to the CXL memory device context Dave Jiang
2023-04-19 20:23 ` [PATCH v4 22/23] cxl: Export sysfs attributes for memory device QTG ID Dave Jiang
2023-04-19 20:23 ` [PATCH v4 23/23] cxl/mem: Add debugfs output for QTG related data Dave Jiang
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