Re: [PATCH v20 5/9] cxl: Update CXL Endpoint AER handler

["Cheatham, Benjamin" <benjamin.cheatham@amd.com>]

On 9/2/2026 8:39 AM, Terry Bowman wrote:
> Rename cxl_error_detected() to cxl_pci_error_detected() and rename the
> struct pci_error_handlers instance from cxl_error_handlers to
> cxl_pci_error_handlers for consistency with the cxl_pci_ prefix used by
> the renamed handler and the rest of the PCI-facing entry points.
> 
> Document the unconditional CXL RAS read policy: on a dead link, readl()
> returns 0xFFFFFFFF which is interpreted as UCE bits set and triggers a
> panic. If RAS registers are not mapped the read is skipped and the
> frozen/perm_failure switch cases defer to AER recovery for devices
> without active CXL.mem traffic.
> 
> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
> Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> Reviewed-by: Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>
> Reviewed-by: Alison Schofield <alison.schofield@intel.com>
> 
> ---
> 
> Changes in v19->v20:
> - Expand the comment block in cxl_pci_error_detected().
> - Clarify commit message's first paragraph. cxl_error_handlers is a variable
> - Clarify AER handling in cxl_pci_error_detected() block comment
> 
> Changes in v18->v19:
> - Add review-by for DaveJ and Jonathan
> - Remove reindent introduced in v18 at cxl_error_handlers definition.
> 
> Changes in v17->v18:
> - Fix cxl_pci_error_detected() to use find_cxl_port_by_uport() and port->uport_dev
> - Read CXL RAS unconditionally; panic on UCE regardless of channel state
> - Document unconditional read policy and 0xFFFFFFFF behavior in comment
> - Drop guard removal paragraph from commit message (not in this diff)
> - Drop Reviewed-by tags pending re-review after message change
> 
> Changes in v16->v17:
> - Rename pci_error_handlers struct instance to cxl_pci_error_handlers for
>   cxl_pci_ naming consistency.
> - Restore scoped_guard(device) and dev->driver check around AER read.
> - NULL-check find_cxl_port_by_dev() before deref of port->uport_dev.
> - Updated commit message. (Terry)
> - Add scope cleanup for port variable in cxl_pci_error_detected() (Terry)
> - Drop cxl_uncor_aer_present(), rely on AER state
> 
> Changes in v15->v16:
> - Update commit message (DaveJ)
> - s/cxl_handle_aer()/cxl_uncor_aer_present()/g (Jonathan)
> - cxl_uncor_aer_present(): Leave original result calculation based on
>   if a UCE is present and the provided state (Terry)
> - Add call to pci_print_aer(). AER fails to log because is upstream
>   link (Terry)
> 
> Changes in v14->v15:
> - Update commit message and title. Added Bjorn's ack.
> - Move CE and UCE handling logic here
> 
> Changes in v13->v14:
> - Add Dave Jiang's review-by
> - Update commit message & headline (Bjorn)
> - Refactor cxl_port_error_detected()/cxl_port_cor_error_detected() to
>   one line (Jonathan)
> - Remove cxl_walk_port() (Dan)
> - Remove cxl_pci_drv_bound(). Check for 'is_cxl' parent port is
>   sufficient (Dan)
> - Remove device_lock_if()
> - Combined CE and UCE here (Terry)
> 
> Changes in v12->v13:
> - Move get_pci_cxl_host_dev() and cxl_handle_proto_error() to Dequeue
>   patch (Terry)
> - Remove EP case in cxl_get_ras_base(), not used. (Terry)
> - Remove check for dport->dport_dev (Dave)
> - Remove whitespace (Terry)
> 
> Changes in v11->v12:
> - Add call to cxl_pci_drv_bound() in cxl_handle_proto_error() and
>   pci_to_cxl_dev()
> - Change cxl_error_detected() -> cxl_cor_error_detected()
> - Remove NULL variable assignments
> - Replace bus_find_device() with find_cxl_port_by_uport() for upstream
>   port searches.
> 
> Changes in v10->v11:
> - None
> ---
>  drivers/cxl/core/ras.c | 25 ++++++++++++++++---------
>  drivers/cxl/cxlpci.h   |  8 ++++----
>  drivers/cxl/pci.c      |  6 +++---
>  3 files changed, 23 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c
> index e99dcd028b738..bf479fac08565 100644
> --- a/drivers/cxl/core/ras.c
> +++ b/drivers/cxl/core/ras.c
> @@ -61,7 +61,7 @@ cxl_cper_trace_uncorr_prot_err(struct cxl_memdev *cxlmd,
>  
>  	/*
>  	 * ras_cap.header_log[] holds CXL_HEADERLOG_SIZE_U32 (16) hardware
> -	 * dwords.  Copy them into the front of a zero-filled
> +	 * dwords. Copy them into the front of a zero-filled

Stray whitespace fix? Doesn't matter much to me, so:

Reviewed-by: Ben Cheatham <benjamin.cheatham@amd.com>