From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1EB47238D42; Wed, 1 Oct 2025 09:50:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759312259; cv=none; b=LxjE1m+6zZQRFqp8ChIBPkyg1sdBBC5864GX1z5yOB16m0D+TMzIpWg+7AeH/Ki5v9omg2OrGQFZRSKLUw+NSgvfApRgNuPwMbVLllcW5P/ufGjszzBqh2HkqPAtNKv7ih2LfzgggDENulG7926WL8tz7+gmaFYQ1bQpPEaJFE0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759312259; c=relaxed/simple; bh=LBzKpvYn50qQRIoPNE9y9HPb+JJBbJm+1xmS3YmjJxs=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=AMUIivuaP6Cx8VWFoFcwQ8X0WDdQaixqwRghaUDapCvnMpBYTL4iBr531fANsZ7JRZeyB+1OTmLzl00zemEuwclOc9CgeGY5OT4IZIGGNwPDyS8KdcLGsi+E6xT4SycFTAWJOtZa5T2W9E53cLA5sjP3EJVcU4Ny0Whno/D7wjU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 01B0516F2; Wed, 1 Oct 2025 02:50:48 -0700 (PDT) Received: from [10.1.197.69] (eglon.cambridge.arm.com [10.1.197.69]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id ECE5A3F59E; Wed, 1 Oct 2025 02:50:50 -0700 (PDT) Message-ID: <7ac224c2-9014-4701-8d96-6df0a4bcc5f6@arm.com> Date: Wed, 1 Oct 2025 10:50:49 +0100 Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 16/29] arm_mpam: Add a helper to touch an MSC from any CPU To: Jonathan Cameron Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org, D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , fenghuay@nvidia.com, baisheng.gao@unisoc.com, Rob Herring , Rohit Mathew , Rafael Wysocki , Len Brown , Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Catalin Marinas , Will Deacon , Greg Kroah-Hartman , Danilo Krummrich , Ben Horgan References: <20250910204309.20751-1-james.morse@arm.com> <20250910204309.20751-17-james.morse@arm.com> <20250912125722.0000373e@huawei.com> Content-Language: en-GB From: James Morse In-Reply-To: <20250912125722.0000373e@huawei.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Hi Jonathan, On 12/09/2025 12:57, Jonathan Cameron wrote: > On Wed, 10 Sep 2025 20:42:56 +0000 > James Morse wrote: > >> Resetting RIS entries from the cpuhp callback is easy as the >> callback occurs on the correct CPU. This won't be true for any other >> caller that wants to reset or configure an MSC. >> >> Add a helper that schedules the provided function if necessary. >> >> Callers should take the cpuhp lock to prevent the cpuhp callbacks from >> changing the MSC state. >> >> Signed-off-by: James Morse >> Reviewed-by: Ben Horgan > Reviewed-by: Jonathan Cameron Thanks! James